Patents by Inventor Cheng-Yuan Tsai

Cheng-Yuan Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180138402
    Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) cell. The RRAM cell has a bottom electrode disposed over a lower interconnect layer and a data storage layer having a first thickness over the bottom electrode. A capping layer is disposed over the data storage layer. The capping layer has a second thickness that is in a range of between approximately 2 and approximately 3 times thicker than the first thickness. A top electrode is disposed over the capping layer and an upper interconnect layer is disposed over the top electrode.
    Type: Application
    Filed: January 15, 2018
    Publication date: May 17, 2018
    Inventors: Trinh Hai Dang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chin-Chieh Yang, Yu-Wen Liao, Wen-Ting Chu, Chia-Shiung Tsai
  • Publication number: 20180122844
    Abstract: The present application relates to a method to simplify the scribe line opening filling processes, and to further improve the surface uniformity of the conductive pad fabrication process. A passivation layer is formed over a semiconductor substrate, and a scribe line opening is formed through the passivation layer and the semiconductor substrate. To fill the scribe line opening, a first dielectric layer is formed within the scribe line opening over the conductive pad and extending over the passivation layer. The first dielectric layer is formed by a selective deposition process such that the first dielectric layer is formed on the conductive pad at a deposition rate greater than that formed on the passivation layer.
    Type: Application
    Filed: October 28, 2016
    Publication date: May 3, 2018
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai, Chih-Hui Huang
  • Patent number: 9960353
    Abstract: Embodiments of forming an image sensor with an organic photodiode are provided. The organic photodiode uses dual electron-blocking layers formed next to the anode of the organic photodiode to reduce dark current. By using dual electron-blocking layers, the values of highest occupied molecular orbital (HOMO) for the neighboring anode layer and the organic electron-blocking layer are matched by one of the dual electron-blocking layers to form a photodiode with good performance. The values of the lowest occupied molecular orbital (LOMOs) of the dual electron-blocking layers are selected to be lower than the neighboring anode layer to reduce dark current.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Wei Liang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chia-Shiung Tsai
  • Patent number: 9960200
    Abstract: The present application relates to a method to simplify the scribe line opening filling processes, and to further improve the surface uniformity of the conductive pad fabrication process. A passivation layer is formed over a semiconductor substrate, and a scribe line opening is formed through the passivation layer and the semiconductor substrate. To fill the scribe line opening, a first dielectric layer is formed within the scribe line opening over the conductive pad and extending over the passivation layer. The first dielectric layer is formed by a selective deposition process such that the first dielectric layer is formed on the conductive pad at a deposition rate greater than that formed on the passivation layer.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai, Chih-Hui Huang
  • Publication number: 20180114935
    Abstract: The present disclosure provides a photosensitive device. The photosensitive device includes a donor-intermix-acceptor (PIN) structure. The PIN structure includes an organic hole transport layer; an organic electron transport layer; and an intermix layer sandwiched between the hole transport organic material layer and the electron transport organic material layer. The intermix layer includes a mixture of an n-type organic material and a p-type organic material.
    Type: Application
    Filed: December 19, 2017
    Publication date: April 26, 2018
    Inventors: Chin-Wei Liang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chia-Shiung Tsai
  • Patent number: 9941398
    Abstract: A semiconductor structure comprises a semiconductive substrate comprising a top surface, a III-V compound layer over the semiconductive substrate, and a first passivation layer over the III-V compound layer. The semiconductor structure also includes an etch stop layer over the first passivation layer. The semiconductor structure further includes a gate stack over the first passivation layer and surrounded by the etch stop layer.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: April 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Han-Chin Chiu, Sheng-De Liu, Yu-Syuan Lin, Yao-Chung Chang, Cheng-Yuan Tsai
  • Publication number: 20180053748
    Abstract: A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.
    Type: Application
    Filed: October 16, 2017
    Publication date: February 22, 2018
    Inventors: Chen-Fa Lu, Cheng-Yuan Tsai, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 9893900
    Abstract: A network apparatus coupled to a plurality of nodes. The nodes are clustered into a plurality of groups. The network apparatus includes a storage component and a controller. The storage component is configured to store a plurality of group numbers corresponding to the groups and a plurality of node numbers corresponding to the nodes. The controller is configured to transmit a broadcast packet to all of the nodes. The broadcast packet includes a local network broadcast message. The local network broadcast message includes operating information. The local network broadcast message corresponds to at least one of the group numbers and the node numbers. Each of the nodes determines whether to dismiss the operating information of the broadcast packet according to the local network broadcast message of the broadcast packet.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: February 13, 2018
    Assignee: DELTA NETWORKS, INC.
    Inventors: Cheng-Yuan Tsai, Shu-Li Chang
  • Patent number: 9893120
    Abstract: The present disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a bottom electrode via (BEVA), a recap layer on the BEVA, and a magnetic tunneling junction (MTJ) layer over the recap layer. The BEVA includes a lining layer over a bottom and a sidewall of a trench of the BEVA, and electroplated copper over the lining layer, filling the trench of the BEVA. The recap layer overlaps a top surface of the lining layer and a top surface of the electroplated copper.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: February 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Harry-Hak-Lay Chuang, Kuei-Hung Shen, Hsun-Chung Kuang, Cheng-Yuan Tsai, Ru-Liang Lee
  • Patent number: 9887134
    Abstract: Semiconductor devices, methods of manufacture thereof, and methods of singulating semiconductor devices are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming a trench in a substrate, the trench being formed within a first side of the substrate and disposed around a portion of the substrate. A first insulating material is formed over the first side of the substrate and the trench, and a second insulating material is formed over the first insulating material. Apertures are formed in the second insulating material and the first insulating material over the portion of the substrate. Features are formed in the apertures, and a carrier is coupled to the features and the second insulating material. A second side of the substrate is planarized, the second side of the substrate being opposite the first side of the substrate. The second insulating material is removed, and the carrier is removed.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: February 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wen Chang, Jian-Shiou Huang, Cheng-Yuan Tsai, Kong-Beng Thei
  • Publication number: 20180033749
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductive substrate and an interconnect structure over the semiconductive substrate. The semiconductor structure also comprises a bond pad in the semiconductive substrate and coupled to the metal layer. The bond pad comprises two conductive layers.
    Type: Application
    Filed: October 6, 2017
    Publication date: February 1, 2018
    Inventors: Sheng-Chau CHEN, Shih-Pei CHOU, Ming-Che LEE, Kuo-Ming WU, Cheng-Hsien CHOU, Cheng-Yuan TSAI, Yuer-Luen TU
  • Patent number: 9876184
    Abstract: The present disclosure provides a photosensitive device. The photosensitive device includes a donor-intermix-acceptor (PIN) structure. The PIN structure includes an organic hole transport layer; an organic electron transport layer; and an intermix layer sandwiched between the hole transport organic material layer and the electron transport organic material layer. The intermix layer includes a mixture of an n-type organic material and a p-type organic material.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: January 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Wei Liang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chia-Shiung Tsai
  • Patent number: 9876167
    Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a good yield, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode over a lower metal interconnect layer, and forming a variable resistance dielectric data storage layer having a first thickness onto the bottom electrode. A capping layer is formed onto the dielectric data storage layer. The capping layer has a second thickness that is in a range of between approximately 2 to approximately 3 times thicker than the first thickness. A top electrode is formed over the capping layer, and an upper metal interconnect layer is formed over the top electrode.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: January 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Trinh Hai Dang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chin-Chieh Yang, Yu-Wen Liao, Wen-Ting Chu, Chia-Shiung Tsai
  • Patent number: 9859323
    Abstract: A complementary metal-oxide-semiconductor (CMOS) image sensor having a passivation layer is provided. The CMOS image sensor includes a sensing device substrate. Isolation structures are positioned within trenches of the sensing device substrate. The isolation structures are arranged along opposing sides of a plurality of image sensing devices. The CMOS image sensor also includes a passivation layer. The passivation layer includes passivation sidewalls arranged along the sidewalls of the isolation structures. A metallic grid overlies the passivation layer. The metallic grid includes a metal framework surrounding openings overlying the plurality of image sensing devices. The passivation layer further includes passivation section underlying the openings.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chau Chen, Cheng-Hsien Chou, Cheng-Yuan Tsai, Sheng-Chan Li, Zhi-Yang Wang
  • Publication number: 20170365514
    Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.
    Type: Application
    Filed: September 1, 2017
    Publication date: December 21, 2017
    Inventors: Chun-Han TSAO, Chih-Ming CHEN, Han-Yu CHEN, Szu-Yu WANG, Lan-Lin CHAO, Cheng-Yuan TSAI
  • Patent number: 9847401
    Abstract: A semiconductor device comprising a substrate, a channel layer over the substrate, an active layer over the channel layer and a laminate layer in contact with the active layer. The active layer has a band gap discontinuity with the channel layer.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: December 19, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Han-Chin Chiu, Hsing-Lien Lin, Cheng-Yuan Tsai
  • Publication number: 20170358620
    Abstract: A complementary metal-oxide-semiconductor (CMOS) image sensor having a passivation layer is provided. The CMOS image sensor includes a sensing device substrate. Isolation structures are positioned within trenches of the sensing device substrate. The isolation structures are arranged along opposing sides of a plurality of image sensing devices. The CMOS image sensor also includes a passivation layer. The passivation layer includes passivation sidewalls arranged along the sidewalls of the isolation structures. A metallic grid overlies the passivation layer. The metallic grid includes a metal framework surrounding openings overlying the plurality of image sensing devices. The passivation layer further includes passivation section underlying the openings.
    Type: Application
    Filed: June 13, 2016
    Publication date: December 14, 2017
    Inventors: Sheng-Chau Chen, Cheng-Hsien Chou, Cheng-Yuan Tsai, Sheng-Chan Li, Zhi-Yang Wang
  • Patent number: 9825117
    Abstract: Some embodiments of the present disclosure provide an integrated circuit (IC) device including a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes a lower metal capacitor electrode, an upper metal capacitor electrode, and a capacitor dielectric separating the lower metal capacitor electrode from the upper metal capacitor electrode. The capacitor dielectric is made up of an amorphous oxide/nitride matrix and a plurality of metal or metal oxide/nitride nano-particles that are randomly distributed over the volume of amorphous oxide/nitride matrix.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: November 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Shiou Huang, Yao-Wen Chang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chia-Shiung Tsai
  • Patent number: 9818885
    Abstract: A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: November 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wen Chang, Cheng-Yuan Tsai, Hsing-Lien Lin
  • Publication number: 20170301728
    Abstract: The present disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a bottom electrode via (BEVA), a recap layer on the BEVA, and a magnetic tunneling junction (MTJ) layer over the recap layer. The BEVA includes a lining layer over a bottom and a sidewall of a trench of the BEVA, and electroplated copper over the lining layer, filling the trench of the BEVA. The recap layer overlaps a top surface of the lining layer and a top surface of the electroplated copper.
    Type: Application
    Filed: April 15, 2016
    Publication date: October 19, 2017
    Inventors: HARRY-HAK-LAY CHUANG, KUEI-HUNG SHEN, HSUN-CHUNG KUANG, CHENG-YUAN TSAI, RU-LIANG LEE