Abstract: A set of physical unclonable function (PUF) cells is configured with a set of capacitive devices in an integrated circuit (IC). A subset of PUF cells includes a corresponding subset of capacitive devices that have failed during fabrication. A charging current sufficient to charge an operational capacitive device in a PUF cell is sent to the set of PUF cells. A determination is made whether an output voltage of a PUF cell exceeds a threshold. When the output voltage exceeding the threshold, a logic value of 1 is produced at a position in a bit-string. The determination and the producing is repeated for each PUF cell in the set to output a bit-string, which includes 1s and 0s in random positions. The bit-string is used in a security application as a random stable value owing to a random pattern of 1s and 0s present in the bit-string.

Abstract: A capacitor structure can include a parallel connection of a plurality of trench capacitors. First nodes of the plurality of trench capacitors are electrically tied to provide a first node of the capacitor structure. Second nodes of the plurality of trench capacitors are electrically tied together through at least one programmable electrical connection at a second node of the capacitor structure. Each programmable electrical connection can include at least one of a programmable electrical fuse and a field effect transistor, and can disconnect a corresponding trench capacitor temporarily or permanently. The total capacitance of the capacitor structure can be tuned by programming, temporarily or permanently, the at least one programmable electrical connection.

Abstract: A method includes forming patterned lines on a substrate having a predetermined pitch. The method further includes forming spacer sidewalls on sidewalls of the patterned lines. The method further includes forming material in a space between the spacer sidewalls of adjacent patterned lines. The method further includes forming another patterned line from the material by protecting the material in the space between the spacer sidewalls of adjacent patterned lines while removing the spacer sidewalls. The method further includes transferring a pattern of the patterned lines and the patterned line to the substrate.

Abstract: A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device.

Abstract: An electrical fuse has an anode contact on a surface of a semiconductor substrate. The electrical fuse has a cathode contact on the surface of the semiconductor substrate spaced from the anode contact. The electrical fuse has a link within the substrate electrically interconnecting the anode contact and the cathode contact. The link comprises a semiconductor layer and a silicide layer. The silicide layer extends beyond the anode contact. An opposite end of the silicide layer extends beyond the cathode contact. A silicon germanium region is embedded in the semiconductor layer under the silicide layer, between the anode contact and the cathode contact.

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a junction butting region using low energy ion implantation to reduce parasitic leakage and body-to-body leakage between adjacent FETs that share a common contact in high density memory technologies, such as dynamic random access memory (DRAM) devices and embedded DRAM (eDRAM) devices. A method disclosed may include forming a junction butting region at the bottom of a trench formed in a semiconductor on insulator (SOI) layer using low energy ion implantation and protecting adjacent structures from damage from ion scattering using a protective layer.

Abstract: The present disclosure generally relates to a wiring structure for a fuse component and corresponding methods of fabrication. A wiring structure for a fuse component according to the present disclosure can include: a first electrical terminal embedded within a doped conductive layer, the doped conductive layer being positioned between two insulator layers of an integrated circuit (IC) structure; a dielectric liner positioned between the first electrical terminal and the doped conductive layer; a second electrical terminal embedded within the doped conductive layer; wherein each of the first electrical terminal and the second electrical terminal are further embedded in one of the two insulator layers, and the dielectric liner is configured to degrade upon becoming electrically charged.

Abstract: A deep trench capacitor structure including an SOI substrate comprising an SOI layer, a rare earth oxide layer, and a bulk substrate, the rare earth oxide layer is located below the SOI layer and above the bulk substrate, and the rare earth oxide layer insulates the SOI layer from the bulk substrate, and a deep trench capacitor extending from a top surface of the SOI layer, through the rare earth oxide layer, down to a location within the bulk substrate, the rare earth oxide layer contacts the deep trench capacitor at an interface between the rare earth oxide layer and the bulk substrate forming an incline away from the deep trench capacitor.

Abstract: A pair of horizontal-step-including trenches are formed in a semiconductor layer by forming a pair of first trenches having a first depth around a gate structure on the semiconductor layer, forming a disposable spacer around the gate structure to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth greater than the first depth. The disposable spacer is removed, and selective epitaxy is performed to form an integrated epitaxial source and source extension region and an integrated epitaxial drain and drain extension region. A replacement gate structure can be formed after deposition and planarization of a planarization dielectric layer and subsequent removal of the gate structure and laterally expand the gate cavity over epitaxial source and drain extension regions. Alternately, a contact-level dielectric layer can be deposited directly on the integrated epitaxial regions and contact via structures can be formed therein.

Abstract: An electronic fuse link with lower programming current for high performance and self-aligned methods of forming the same. The invention provides a horizontal e-fuse structure in the middle of the line. A reduced fuse link width is achieved by spacers on sides of pair of dummy or active gates, to create sub-lithographic dimension between gates with spacers to confine a fuse link. A reduced height in the third dimension on the fuse link achieved by etching the link, thereby creating a fuse link having a sub-lithographic size in all dimensions. The fuse link is formed over an isolation region to enhanced heating and aid fuse blow.

Abstract: In a vertical dynamic memory cell, monocrystalline semiconductor material of improved quality is provided for the channel of an access transistor by lateral epitaxial growth over an insulator material (which complements the capacitor dielectric in completely surrounding the storage node except at a contact connection structure, preferably of metal, from the access transistor to the storage node electrode) and etching away a region of the lateral epitaxial growth including a location where crystal lattice dislocations are most likely to occur; both of which features serve to reduce or avoid leakage of charge from the storage node. An isolation structure can be provided in the etched region such that space is provided for connections to various portions of a memory cell array.

Abstract: A pair of horizontal-step-including trenches are formed in a semiconductor layer by forming a pair of first trenches having a first depth around a gate structure on the semiconductor layer, forming a disposable spacer around the gate structure to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth greater than the first depth. The disposable spacer is removed, and selective epitaxy is performed to form an integrated epitaxial source and source extension region and an integrated epitaxial drain and drain extension region. A replacement gate structure can be formed after deposition and planarization of a planarization dielectric layer and subsequent removal of the gate structure and laterally expand the gate cavity over expitaxial source and drain extension regions. Alternately, a contact-level dielectric layer can be deposited directly on the integrated epitaxial regions and contact via structures can be formed therein.

Abstract: A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device.

Abstract: A node dielectric and a conductive trench fill region filling a deep trench are recessed to a depth that is substantially coplanar with a top surface of a semiconductor-on-insulator (SOI) layer. A shallow trench isolation portion is formed on one side of an upper portion of the deep trench, while the other side of the upper portion of the deep trench provides an exposed surface of a semiconductor material of the conductive fill region. A selective epitaxy process is performed to deposit a raised source region and a raised strap region. The raised source region is formed directly on a planar source region within the SOI layer, and the raised strap region is formed directly on the conductive fill region. The raised strap region contacts the raised source region to provide an electrically conductive path between the planar source region and the conductive fill region.

Abstract: A dielectric template layer is deposited on a substrate. Line trenches are formed within the dielectric template layer by an anisotropic etch that employs a patterned mask layer. The patterned mask layer can be a patterned photoresist layer, or a patterned hard mask layer that is formed by other image transfer methods. A lower portion of each line trench is filled with an epitaxial rare-earth oxide material by a selective rare-earth oxide epitaxy process. An upper portion of each line trench is filled with an epitaxial semiconductor material by a selective semiconductor epitaxy process. The dielectric template layer is recessed to form a dielectric material layer that provides lateral electrical isolation among fin structures, each of which includes a stack of a rare-earth oxide fin portion and a semiconductor fin portion.

Abstract: A method of forming a semiconductor device including forming well trenches on opposing sides of a gate structure by removing portions of a semiconductor on insulator (SOI) layer of an semiconductor on insulator (SOI) substrate, wherein the base of the well trenches is provided by a surface of a buried dielectric layer of the SOI substrate and sidewalls of the well trenches are provided by a remaining portion of the SOI layer. Forming a dielectric fill material at the base of the well trenches, wherein the dielectric fill material is in contact with the sidewalls of the well trenches and at least a portion of the surface of the buried dielectric layer that provides the base of the well trenches. Forming a source region and a drain region in the well trenches with an in-situ doped epitaxial semiconductor material.

Abstract: A method of fabricating a material having nanoscale pores is provided. In one embodiment, the method of fabricating a material having nanoscale pores may include providing a single crystal semiconductor. The single crystal semiconductor layer is then patterned to provide an array of exposed portions of the single crystal semiconductor layer having a width that is equal to the minimum lithographic dimension. The array of exposed portion of the single crystal semiconductor layer is then etched using an etch chemistry having a selectivity for a first crystal plane to a second crystal plane of 100% or greater. The etch process forms single or an array of trapezoid shaped pores, each of the trapezoid shaped pores having a base that with a second width that is less than the minimum lithographic dimension.

Abstract: Dummy deep trenches can be formed within a logic device region in which logic devices are to be formed while deep trench capacitors are formed within a memory device region. Semiconductor fins are formed over a top surface prior to forming trenches, and disposable material is filled around said semiconductor fins. A top surface of said disposable filler material layer can be coplanar with a top surface of said semiconductor fins, which eases deep trench formation. Conductive material portions of the dummy deep trenches can be recessed to avoid electrical contact with semiconductor fins within the logic device region, while an inner electrode of each deep trench can contact a semiconductor fin within the memory device region. A dielectric material portion can be formed above each conductive material portion of a dummy deep trench.

Abstract: A trench capacitor and method of fabrication are disclosed. The SOI region is doped such that a selective isotropic etch used for trench widening does not cause appreciable pullback of the SOI region, and no spacers are needed in the upper portion of the trench.

Abstract: After formation of a gate stack, regions in which a source and a drain are to be formed are recessed through the top semiconductor layer and into an upper portion of a buried single crystalline rare earth oxide layer of a semiconductor-on-insulator (SOI) substrate so that a source trench and drain trench are formed. An embedded single crystalline semiconductor portion epitaxially aligned to the buried single crystalline rare earth oxide layer is formed in each of the source trench and the drain trench to form a recessed source and a recessed drain, respectively. Protrusion of the recessed source and recessed drain above the bottom surface of a gate dielectric can be minimized to reduce parasitic capacitive coupling with a gate electrode, while providing low source resistance and drain resistance through the increased thickness of the recessed source and recessed drain relative to the thickness of the top semiconductor layer.