High performance CMOS devices and methods for making same
An integrated circuit having high performance CMOS devices with good short channel effects may be made by forming a gate structure over a substrate; forming pocket implant regions and source/drain extensions in the substrate; forming spacers along sides of the gate structure; and thermal annealing the substrate when forming the spacers, the thermal annealing performed at an ultra-low temperature. An integrated circuit having high performance CMOS devices with low parasitic junction capacitance may be made by forming a gate structure over a substrate; forming pocket implant regions and source/drain extensions in the substrate; forming spacers along sides of the gate structure; performing a low dosage source/drain implant; and performing a high dosage source/drain implant.
The present invention relates to integrated circuits and high performance complementary metal oxide semiconductor (CMOS) devices and more particularly, to integrated circuits having high performance CMOS devices with good short channel effects, low parasitic junction capacitances, and low junction leakage currents and methods for making same.
BACKGROUND OF THE INVENTIONHigh performance CMOS devices should have, among other characteristics, good short channel behavior, low parasitic junction capacitances and low junction leakage currents. However, as the size of integrated circuits (ICs) continues to shrink and the number of high performance CMOS devices on IC chips continue to increase, the dimensions of the CMOS devices must be scaled down. The scaling down of CMOS devices makes it difficult to achieve good short channel effects, low parasitic junction capacitances and low junction leakage currents.
Accordingly, methods are needed for manufacturing smaller ICs with scaled down high performance CMOS devices.
SUMMARY OF THE INVENTIONIntegrated circuits having high performance CMOS devices with good short channel effects, low parasitic junction capacitances, and low junction leakage currents and methods for making same are disclosed. One of the methods comprises the steps of: forming a gate structure over a substrate; forming pocket implant regions and source/drain extensions in the substrate; forming spacers along sides of the gate structure; and thermal annealing the substrate when forming the spacers, the thermal annealing performed at an ultra-low temperature.
Another one of the methods comprises the steps of: forming a gate structure over a substrate; forming source/drain extensions in the substrate; and performing a thermal cycle process for solid phase epitaxy on the substrate.
Still another one of the methods comprises the steps of: forming a gate structure over a substrate; forming pocket implant regions in the substrate; forming thin, off-set spacers along sides of the gate structure; and forming source/drain extensions in the substrate.
A further one of the methods comprises the steps of: forming a gate structure over a substrate; forming pocket implant regions and source/drain extensions in the substrate; forming spacers along sides of the gate structure; performing a low dosage source/drain implant; and performing a high dosage source/drain implant.
One of the integrated circuits comprises: a gate structure over a substrate; pocket implant regions and source/drain extensions in the substrate; and spacers disposed along sides of the gate structure, the spacers formed while thermal annealing the substrate at an ultra-low temperature.
Another one of the integrated circuits comprises: a gate structure over a substrate; pocket implant regions and source/drain extensions in the substrate; graded source/drain regions in the substrate, the graded source/drain regions formed by a low dosage source/drain implant and a high dosage source/drain implant.
Still another one of the integrated circuits comprises: a gate structure over a substrate; a super halo-shape pocket implant region in the substrate; thin, off-set spacers disposed along sides of the gate structure; and source/drain extensions in the substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
As illustrated in
As illustrated in
As illustrated in
In an alternative embodiment, the UL-DT spacer process is performed in a single step, i.e., during spacer deposition, which operates to thermally anneal the substrate 120 at an ultra-low temperature between about 350° C. and about 800° C., for a time period ranging between about 5 seconds and about 700 minutes.
As illustrated in
A self-aligning source/drain extension ion implantation process is performed, as illustrated in
The substrate is then subjected to a low temperature thermal cycle process for solid phase epitaxy. The low temperature thermal cycle process activates the dopants forming the source/drain extensions 250a, 250b. The thermal anneal may be performed using RTA or a furnace anneal at an ultra-low temperature between about 350° C. and 800° C. for a time period ranging between about 5 seconds and about 700 minutes.
As illustrated in
A thermal anneal is then performed on the substrate 320. The temperature thermal anneal is performed at a range of about 700° C. to about 1050° C., for a time period of about 0 seconds to about 60 seconds to activate the pocket dopant.
A self-aligning source/drain extension ion implantation process is performed, as illustrated in
The substrate 320 is then subjected to a low temperature thermal cycle process for solid phase epitaxy. The low temperature thermal cycle process activates the dopants forming the source/drain extensions 350a, 350b. The thermal anneal is performed at an ultra-low temperature between about 350° C. and 800° C., for a time period of between about 5 seconds to about 700 minutes.
As illustrated in
First and second non-conductive offset, thin-width spacers 462a, 462b are then formed along opposing side walls of the gate structure 430, as illustrated in
After offset spacer process, a self-aligning source/drain extension ion implantation process is performed, as illustrated in
As illustrated in
CMOS devices fabricated in accordance with the above methods exhibit improved short channel effects and low leakage currents. More specifically, the shallow and lightly doped source/drain extensions minimize the short channel behavior as the CMOS devices are scaled down. In addition, the implant pocket region or regions reduce the leakage current of the CMOS device.
As illustrated in
First and second non-conductive spacers 560a, 560b are then formed along opposing side walls of the gate structure 530 as illustrated in
As illustrated in
The high-energy, low-dose source/drain implant may be performed with a beam tilt angle up to about 50 degrees. The implant energy is typically less than 150 kev and the implant dosage is typically less than 1E15 cm−2. The dopant used may include, for example, As, P, BF2, In Sb, and B.
The high-dose source/drain implant may be performed with a beam tilt angle up to about 50 degrees. The implant energy is typically greater than 1 kev and the implant dosage is typically greater than 1E14 cm−2. The dopant used may include, for example, As, P, BF2, In Sb, and B.
After completion of the smart grading source/drain implantation process, a silicidation process may be performed to form conductive silicide films 580a, 580b, 580c over the gate conductor 534 and source/drain regions 570a, 570b, as illustrated in
While the foregoing invention has been described with reference to the above, various modifications and changes can be made without departing from the spirit of the invention. Accordingly, all such modifications and changes are considered to be within the scope of the appended claims.
Claims
1. A method of manufacturing an integrated circuit, the method comprising the steps of:
- forming a gate structure over a substrate;
- forming pocket implant regions and source/drain extensions in the substrate;
- forming spacers along sides of the gate structure; and
- thermal annealing the substrate when forming the spacers, the thermal annealing performed at an ultra-low temperature.
2. The method according to claim 1, wherein the gate structure comprises a gate conductor composed of a material selected from the group consisting of poly-Si, poly SiGe, metal, metal oxide, metal nitride, silicide and combinations thereof.
3. The method according to claim 1, wherein the ultra-low temperature is between about 350° C. and about 800° C.
4. The method according to claim 1, wherein the thermal annealing step is performed for a time period of between about 5 seconds and about 700 minutes.
5. An integrated circuit comprising:
- a gate structure over a substrate;
- pocket implant regions and source/drain extensions in the substrate; and
- spacers disposed along sides of the gate structure, the spacers formed while thermal annealing the substrate at an ultra-low temperature.
6. The integrated circuit according to claim 5, wherein the gate structure comprises a gate conductor composed of a material selected from the group consisting of poly-Si, poly SiGe, metal, metal oxide, metal nitride, silicide and combinations thereof.
7. The integrated circuit according to claim 5, wherein the ultra-low temperature is between about 350° C. and about 800° C.
8. The integrated circuit according to claim 5, wherein the thermal annealing step is performed for a time period of between about 5 seconds and about 700 minutes.
9. A method of manufacturing an integrated circuit, the method comprising the steps of:
- forming a gate structure over a substrate;
- forming source/drain extensions in the substrate; and
- performing a thermal cycle process for solid phase epitaxy on the substrate.
10. The method according to claim 9, further comprising the step of thermal annealing the substrate at an ultra-low temperature.
11. The method according to claim 10, wherein the ultra-low temperature is between about 350° C. and about 800° C.
12. The method according to claim 9, further comprising the step of forming pocket implant regions in the substrate.
13. The method according to claim 12, further comprising the step of thermal annealing the substrate at an ultra-low temperature.
14. The method according to claim 13, wherein the ultra-low temperature is between about 350° C. and about 800° C.
15. The method according to claim 12, wherein the step of forming pocket implant regions in the substrate is performed prior to the step of forming source/drain implant regions in the substrate.
16. The method according to claim 13, wherein the thermal annealing step is performed after the step of forming the pocket implant regions and before the step of forming the source/drain extensions.
17. The method according to claim 10, wherein the thermal annealing step is performed after the step of performing a thermal cycle process for solid phase epitaxy.
18. A method of manufacturing an integrated circuit, the method comprising the steps of:
- forming a gate structure over a substrate;
- forming a super halo-shape pocket implant region in the substrate;
- forming thin, off-set spacers along sides of the gate structure; and
- forming source/drain extensions in the substrate.
19. A method of manufacturing an integrated circuit, the method comprising the steps of:
- forming a gate structure over a substrate;
- forming pocket implant regions and source/drain extensions in the substrate;
- forming spacers along sides of the gate structure;
- performing a low dosage source/drain implant; and
- performing a high dosage source/drain implant.
20. The method according to claim 19, wherein the low dosage source/drain implant is performed at a high energy.
21. The method according to claim 20, wherein the high energy comprises less than 150 kev.
22. The method according to claim 19, wherein the low dosage source/drain implant is performed with a dopant dosage of less than 1E15 cm−2.
23. The method according to claim 22, wherein the high dosage source/drain implant is performed with a dopant dosage of greater than 1E14 cm−2.
24. The method according to claim 19, wherein the high dosage source/drain implant is performed with a dopant dosage of greater than 1E14 cm−2.
25. An integrated circuit comprising:
- a gate structure over a substrate;
- pocket implant regions and source/drain extensions in the substrate; and
- graded source/drain regions in the substrate, the graded source/drain regions formed by a low dosage source/drain implant and a high dosage source/drain implant.
26. The integrated circuit according to claim 25, wherein the low dosage source/drain implant is performed at a high energy.
27. The integrated circuit according to claim 26, wherein the high energy comprises less than 150 kev.
28. The integrated circuit according to claim 25, wherein the low dosage source/drain implant is performed with a dopant dosage of less than 1E15 cm−2.
29. The integrated circuit according to claim 28, wherein the high dosage source/drain implant is performed with a dopant dosage of greater than 1E14 cm−2.
30. The integrated circuit according to claim 25, wherein the high dosage source/drain implant is performed with a dopant dosage of greater than 1E14 cm−2.
31. An integrated circuit comprising:
- a gate structure over a substrate;
- a super halo-shape pocket implant region in the substrate;
- thin, off-set spacers disposed along sides of the gate structure; and
- source/drain extensions in the substrate.
Type: Application
Filed: Nov 30, 2004
Publication Date: Jun 1, 2006
Inventors: Chih-Hao Wan (Hsinchu), Ta-Wei Wang (Taipei), Chenming Hu (Almo, CA)
Application Number: 10/999,724
International Classification: H01L 21/336 (20060101); H01L 29/94 (20060101);