METHOD FOR FORMING A SPLIT GATE DEVICE
A method for forming a semiconductor device includes forming a dielectric layer over a substrate. The method further includes forming a select gate layer over the dielectric layer. The method further includes etching the select gate layer at a first etch rate to form a first portion of a sidewall of a select gate, wherein the step of etching the select gate layer at the first etch rate includes using an oxidizing agent to oxidize at least a top portion of the substrate underlying the dielectric layer to form an oxide layer. The method further includes etching the select gate layer at a second etch rate lower than the first etch rate to form a second portion of the sidewall of the select gate, wherein the step of etching the select gate layer at the second etch rate includes removing only a top portion of the dielectric layer.
1. Field
This disclosure relates generally to semiconductor processing, and more specifically, to split gate devices.
2. Related Art
Split gate devices, which include both a select gate and a control gate, are typically used as bitcell storage devices within nonvolatile memory arrays. The use of a separate select gate for the bitcells in such arrays allows for improved isolation and reduced bitcell disturb during programming and reading of the bitcells. For example, program disturb is reduced for memory cells that are unselected but are either on the selected row or, in the alternative, on the selected column. Normally, cells on the selected row or the selected column are the most likely to be a problem for disturb regardless of the operation that is being performed on a selected cell. With the split gate memory cell having substantially solved the program disturb problem for cells on the selected rows or columns, a disturb problem with cells on unselected rows and unselected columns has become significant. One of the reasons is that the particular stress that is applied for cells on unselected rows and columns is applied for many more cycles than for a stress that is applied for cells on a selected row or column. Also, due to the length of the select gates and control gates, reduced drive current is obtained which degrades reading performance.
The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
As described above, split gate devices are useful as bitcells in a memory. One embodiment described herein includes a method for forming a split gate device which may allow for improved performance. For example, in one embodiment, a split gate device includes a shallow recessed region adjacent a sidewall of the select gate in which portions of the charge storage layer and the control gate are formed. Also, in one embodiment, a split gate device includes a shallow recessed region adjacent a sidewall of the select gate in which portions of the charge storage layer and the control gate are formed.
Therefore, a substantially completed nanocrystal split gate device (also referred to as a split gate bitcell) is illustrated in
Therefore, a substantially completed nanocrystal split gate device (also referred to as a split gate bitcell) is illustrated in
By now it should be appreciated that there has been provided a method for forming a nanocrystal split gate device useful as a bitcell in a memory. Through the use of shallow or deep recessed regions which may allow for rounded corners and for a thicker oxide beneath the nanocrystals, an improved split gate device may be achieved.
Although the invention has been described with respect to specific conductivity types or polarity of potentials, skilled artisans appreciated that conductivity types and polarities of potentials may be reversed.
Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, different thin charge storage layers may be used, spacers (such as spacer 22) may be left within the final device, or two devices which share a source/drain region may be formed. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles.
Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.
The following are various embodiments of the present invention.
Item 1 includes a method for forming a semiconductor device including forming a dielectric layer over a substrate; forming a select gate layer over the dielectric layer; etching the select gate layer at a first etch rate to form a first portion of a sidewall of a select gate, wherein the step of etching the select gate layer at the first etch rate includes using an oxidizing agent to oxidize at least a top portion of the substrate underlying the dielectric layer to form an oxide layer below the dielectric layer; and etching the select gate layer at a second etch rate lower than the first etch rate to form a second portion of the sidewall of the select gate, wherein the step of etching the select gate layer at the second etch rate includes removing only a top portion of the dielectric layer. Item 2 includes the method of item 1, wherein the oxidizing agent is selected from a group consisting of oxygen and helium oxide. Item 3 includes the method of item 1, and further includes removing the oxide layer and any remaining portion of the dielectric layer to expose a portion of the substrate; forming a charge storage layer overlying exposed portion of the substrate and the sidewall of the select gate; forming a control gate layer overlying the charge storage layer; and forming a control gate by patterning the control gate layer and the charge storage layer. Item 4 includes the method of item 3, wherein the step of forming the charge storage layer comprises forming a layer of one of a group consisting of nanocrystals, nitride, and oxide. Item 5 includes the method of item 1, wherein the step of etching the select gate layer at the first etch rate comprises using a RF plasma at a first etch power and the step of etching the select gate layer at the second etch rate comprises using the RF plasma at a second etch power lower than the first etch power. Item 6 includes the method of item 1, wherein the step of etching the select gate layer at the first etch rate comprises using a RF plasma at a first etch bias and the step of etching the select gate layer at the second etch rate comprises using the RF plasma at a second etch bias lower than the first etch bias. Item 7 includes the method of item 1, wherein the step of etching the select gate layer at the first etch rate comprises using a first etch chemistry and the step of etching the select gate layer at the second etch rate comprises using a second etch chemistry, wherein the second etch chemistry is different from the first etch chemistry. Item 8 includes the method of item 1 and further includes removing the oxide layer and any remaining portion of the dielectric layer to form a recess in the substrate adjacent to the sidewall of the select gate.
Item 9 includes a method for forming a semiconductor device including forming a dielectric layer over a substrate; forming a select gate layer over the dielectric layer; using a first etch chemistry etching the select gate layer at a first etch rate to form a sidewall of a select gate; using a second etch chemistry different from the first etch chemistry, selectively etching the dielectric layer; and etching the substrate at a second etch rate lower than the first etch rate to form a recess in the substrate adjacent to the sidewall of the select gate, wherein the step of etching the substrate at the second etch rate includes using an oxidizing agent. Item 10 includes the method of item 9, wherein the oxidizing agent is selected from a group consisting of oxygen and helium oxide. Item 11 includes the method of item 9 and further includes forming a charge storage layer overlying any exposed portion of the substrate and the sidewall of the select gate; forming a control gate layer overlying the charge storage layer; and forming a control gate by patterning the control gate layer and the charge storage layer. Item 12 includes the method of item 11, wherein the step of forming the charge storage layer comprises forming a layer of one of a group consisting of nanocrystals, nitride, and oxide. Item 12 includes the method of item 9, wherein the step of etching the select gate layer at the first etch rate comprises using a RF plasma at a first etch power and the step of etching the substrate at the second etch rate comprises using the RF plasma at a second etch power lower than the first etch power. Item 14 includes the method of item 9, wherein the step of etching the select gate layer at the first etch rate comprises using a RF plasma at a first etch bias and the step of etching the substrate at the second etch rate comprises using the RF plasma at a second etch bias lower than the first etch bias. Item 15 includes the method of item 9, wherein the step of etching the substrate at the second etch rate comprises using a third etch chemistry, wherein the third etch chemistry is different from the first etch chemistry. Item 16 includes the method of item 9, wherein the step of etching the substrate at a second etch rate lower than the first etch rate to form the recess in the substrate comprises forming a substantially vertical recess.
Item 17 includes a method for forming a semiconductor device including forming a dielectric layer over a substrate; forming a select gate layer over the dielectric layer; etching the select gate layer at a first etch rate to form a first portion of a sidewall of a select gate, wherein the step of etching the select gate layer at the first etch rate includes using an oxidizing agent to oxidize at least a top portion of the substrate underlying the dielectric layer to form an oxide layer below the dielectric layer; etching the select gate layer at a second etch rate lower than the first etch rate to form a second portion of the sidewall of the select gate, wherein the step of etching the select gate layer at the second etch rate includes removing only a top portion of the dielectric layer; using a wet etch removing the oxide layer and any remaining portion of the dielectric layer to expose a portion of the substrate; forming a charge storage layer overlying exposed portion of the substrate and the sidewall of the select gate; forming a control gate layer overlying the charge storage layer; and forming a control gate by patterning the control gate layer and the charge storage layer. Item 18 includes the method of item 17, wherein the oxidizing agent is selected from a group consisting of oxygen and helium oxide. Item 19 includes the method of item 18, wherein the step of forming the charge storage layer comprises forming a layer of one of a group consisting of nanocrystals, nitride, and oxide. Item 20 includes the method of item 19, wherein the second etch rate is lower than the first etch rate as a result of a variation in at least one of an etch power, an etch bias, and an etch chemistry associated with a respective etching step.
Claims
1. A method for forming a semiconductor device, the method comprising:
- forming a dielectric layer over a substrate;
- forming a select gate layer over the dielectric layer;
- etching the select gate layer at a first etch rate to form a first portion of a sidewall of a select gate, wherein the step of etching the select gate layer at the first etch rate includes using an oxidizing agent to oxidize at least a top portion of the substrate underlying the dielectric layer to form an oxide layer below the dielectric layer; and
- etching the select gate layer at a second etch rate lower than the first etch rate to form a second portion of the sidewall of the select gate, wherein the step of etching the select gate layer at the second etch rate includes removing only a top portion of the dielectric layer.
2. The method of claim 1, wherein the oxidizing agent is selected from a group consisting of oxygen and helium oxide.
3. The method of claim 1 further comprising:
- removing the oxide layer and any remaining portion of the dielectric layer to expose a portion of the substrate;
- forming a charge storage layer overlying exposed portion of the substrate and the sidewall of the select gate;
- forming a control gate layer overlying the charge storage layer; and
- forming a control gate by patterning the control gate layer and the charge storage layer.
4. The method of claim 3, wherein the step of forming the charge storage layer comprises forming a layer of one of a group consisting of nanocrystals, nitride, and oxide.
5. The method of claim 1, wherein the step of etching the select gate layer at the first etch rate comprises using a RF plasma at a first etch power and the step of etching the select gate layer at the second etch rate comprises using the RF plasma at a second etch power lower than the first etch power.
6. The method of claim 1, wherein the step of etching the select gate layer at the first etch rate comprises using a RF plasma at a first etch bias and the step of etching the select gate layer at the second etch rate comprises using the RF plasma at a second etch bias lower than the first etch bias.
7. The method of claim 1, wherein the step of etching the select gate layer at the first etch rate comprises using a first etch chemistry and the step of etching the select gate layer at the second etch rate comprises using a second etch chemistry, wherein the second etch chemistry is different from the first etch chemistry.
8. The method of claim 1 further comprising removing the oxide layer and any remaining portion of the dielectric layer to form a recess in the substrate adjacent to the sidewall of the select gate.
9. A method for forming a semiconductor device, the method comprising:
- forming a dielectric layer over a substrate;
- forming a select gate layer over the dielectric layer;
- using a first etch chemistry etching the select gate layer at a first etch rate to form a sidewall of a select gate;
- using a second etch chemistry different from the first etch chemistry, selectively etching the dielectric layer; and
- etching the substrate at a second etch rate lower than the first etch rate to form a recess in the substrate adjacent to the sidewall of the select gate, wherein the step of etching the substrate at the second etch rate includes using an oxidizing agent.
10. The method of claim 9, wherein the oxidizing agent is selected from a group consisting of oxygen and helium oxide.
11. The method of claim 9 further comprising:
- forming a charge storage layer overlying any exposed portion of the substrate and the sidewall of the select gate;
- forming a control gate layer overlying the charge storage layer; and
- forming a control gate by patterning the control gate layer and the charge storage layer.
12. The method of claim 11, wherein the step of forming the charge storage layer comprises forming a layer of one of a group consisting of nanocrystals, nitride, and oxide.
13. The method of claim 9, wherein the step of etching the select gate layer at the first etch rate comprises using a RF plasma at a first etch power and the step of etching the substrate at the second etch rate comprises using the RF plasma at a second etch power lower than the first etch power.
14. The method of claim 9, wherein the step of etching the select gate layer at the first etch rate comprises using a RF plasma at a first etch bias and the step of etching the substrate at the second etch rate comprises using the RF plasma at a second etch bias lower than the first etch bias.
15. The method of claim 9, wherein the step of etching the substrate at the second etch rate comprises using a third etch chemistry, wherein the third etch chemistry is different from the first etch chemistry.
16. The method of claim 9, wherein the step of etching the substrate at a second etch rate lower than the first etch rate to form the recess in the substrate comprises forming a substantially vertical recess.
17. A method for forming a semiconductor device, the method comprising:
- forming a dielectric layer over a substrate;
- forming a select gate layer over the dielectric layer;
- etching the select gate layer at a first etch rate to form a first portion of a sidewall of a select gate, wherein the step of etching the select gate layer at the first etch rate includes using an oxidizing agent to oxidize at least a top portion of the substrate underlying the dielectric layer to form an oxide layer below the dielectric layer;
- etching the select gate layer at a second etch rate lower than the first etch rate to form a second portion of the sidewall of the select gate, wherein the step of etching the select gate layer at the second etch rate includes removing only a top portion of the dielectric layer;
- using a wet etch removing the oxide layer and any remaining portion of the dielectric layer to expose a portion of the substrate;
- forming a charge storage layer overlying exposed portion of the substrate and the sidewall of the select gate;
- forming a control gate layer overlying the charge storage layer; and
- forming a control gate by patterning the control gate layer and the charge storage layer.
18. The method of claim 17, wherein the oxidizing agent is selected from a group consisting of oxygen and helium oxide.
19. The method of claim 18, wherein the step of forming the charge storage layer comprises forming a layer of one of a group consisting of nanocrystals, nitride, and oxide.
20. The method of claim 19, wherein the second etch rate is lower than the first etch rate as a result of a variation in at least one of an etch power, an etch bias, and an etch chemistry associated with a respective etching step.
Type: Application
Filed: Apr 14, 2010
Publication Date: Oct 20, 2011
Inventors: Sung-Taeg Kang (Austin, TX), Cheong Min Hong (Austin, TX), Brian A. Winstead (Austin, TX)
Application Number: 12/760,313
International Classification: H01L 21/336 (20060101);