Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.

Abstract: A device includes creating an opening in a dielectric layer that is disposed over a bottom electrode layer. A top electrode layer is disposed over the dielectric layer. A magnetic tunnel junction (MTJ) layer is formed in the opening over the bottom electrode layer.

Abstract: A method of fabricating a semiconductor device includes forming a stack of film comprising an anti-ferromagnetic layer, the pin layer, a barrier layer, a free layer and a bottom electrode layer. The method also includes forming a first patterned hard mask over the anti-ferromagnetic layer, etching the anti-ferromagnetic layer and the pin layer by using the first patterned hard mask as a first etch mask, forming a first capping layer along sidewalls of the anti-ferromagnetic layer and the pin layer, etching the barrier layer and the free layer by using first patterned hard mask and the first capping layer as a second etch mask, forming a second capping layer over the first capping layer and extending along sidewalls of the barrier layer and the free layer, exposing the anti-ferromagnetic layer and forming a top electrode layer over the exposed anti-ferromagnetic layer.

Abstract: A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region, where the capacitor is over the semiconductor device. The semiconductor arrangement also includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where the first electrode is substantially larger than other portions of the capacitor.

Abstract: A magnetoresistive random access memory (MRAM) structure includes a bottom electrode structure. A magnetic tunnel junction (MTJ) element is over the bottom electrode structure. The MTJ element includes an anti-ferromagnetic material layer. A ferromagnetic pinned layer is over the anti-ferromagnetic material layer. A tunneling layer is over the ferromagnetic pinned layer. A ferromagnetic free layer is over the tunneling layer. The ferromagnetic free layer has a first portion and a demagnetized second portion. The MRAM also includes a top electrode structure over the first portion.

Abstract: A method of fabricating a metal-insulator-metal (MIM) capacitor structure on a substrate includes forming a patterned metal layer over the substrate; forming an insulator layer over the patterned metal layer; forming a second metal layer over the insulator layer; removing part of the insulating layer and part of the second metal layer thereby forming a substantially coplanar surface that is formed by the patterned metal layer, the insulator layer, and the second metal layer; removing a portion of the second metal layer and a portion of the patterned metal layer to form a fin from the insulator layer that protrudes beyond the first metal layer and the second metal layer; and forming an inter-metal dielectric layer over the fin.

Abstract: A magnetoresistive random access memory (MRAM) device comprises a bottom electrode over a tapered bottom via, a tapered magnetic tunnel junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and a top via over the top electrode. The top via, top electrode, MTJ, bottom electrode, and bottom via (and electrical interfaces therebetween) are substantially aligned along a common vertical axis. The bottom via has a taper angle of about 120° to about 150°. The MTJ has a taper angle of about 70° to about 85°. The MTJ is isolated and protected with dual sidewall spacers.

Abstract: A magnetoresistive random-access memory (MRAM) cell with a dual sidewall spacer structure is provided. The MRAM cell includes an anti-ferromagnetic layer, a pin layer, a free layer, a first sidewall spacer layer, and a second sidewall spacer layer. The pin layer is arranged over the anti-ferromagnetic layer and has a fixed magnetic polarity. The free layer is arranged over the pin layer and has a variable magnetic polarity. The first sidewall spacer layer extends from over the pin layer along sidewalls of the free layer. The second sidewall spacer layer extends from over the anti-ferromagnetic layer along sidewalls of the pin layer and the first sidewall spacer layer. A method for manufacturing the MRAM cell is also provided.

Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor having a first electrode layer, a second electrode layer, and an insulating layer between the first electrode layer and the second electrode layer. At least three dielectric layers are between a bottom surface of the capacitor and the active region.

Abstract: A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region. The semiconductor arrangement includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where an electrode unit of the first electrode has a first portion and a second portion, and where the second portion is above the first portion and is wider than the first portion.

Abstract: A storage device includes a first electrode, a second electrode, a storage element, a spacer and a barrier structure. The second electrode is opposite to the first electrode. The storage element is disposed between the first electrode and the second electrode. The spacer is formed on a sidewall of the second electrode, and the spacer has a notch positioned on a top surface of the spacer. The barrier structure is embedded in a lateral of the spacer, and the barrier structure has a top extending upwards past a bottom of the notch. In addition, a method of manufacturing the storage device is disclosed as well.

Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.

Abstract: A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region, where the capacitor is over the semiconductor device. The semiconductor arrangement also includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where the first electrode is substantially larger than other portions of the capacitor.

Abstract: The present disclosure relates to a magneto-resistive random access memory (MRAM) cell having an extended upper electrode, and a method of formation. In some embodiments, the MRAM cell has a magnetic tunnel junction (MTJ) arranged over a conductive lower electrode. A conductive upper electrode is arranged over the magnetic tunnel junction. The conductive upper electrode has a lower portion and an upper portion. The lower portion overlies the magnetic tunnel junction and is laterally surrounded by an encapsulation structure. The upper portion is arranged onto the lower portion and the encapsulation structure, and laterally extends past the lower portion of the conductive upper electrode. By laterally extending past the lower portion, the upper portion of the conductive upper electrode gives a via a larger landing area than the lower portion of the upper electrode would provide, thereby mitigating via punch through resulting from overlay errors.

Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor having a first electrode layer, a second electrode layer, and an insulating layer between the first electrode layer and the second electrode layer. At least three dielectric layers are between a bottom surface of the capacitor and the active region.

Abstract: A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer.

Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a bottom electrode having a first width and a dielectric structure having a second width formed over the bottom electrode. The semiconductor structure further includes a top electrode having a third width formed over the dielectric structure. In addition, the second width of the dielectric structure is greater than the first width of the bottom electrode.

Abstract: A magnetoresistive random-access memory (MRAM) cell with a dual sidewall spacer structure is provided. The MRAM cell includes <claim 1>. A method for manufacturing the MRAM cell is also provided.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first electrode over the semiconductor substrate. The first electrode has a ring-shaped cross section. The semiconductor device structure also includes a resistance-switching layer over the first electrode and a second electrode over the resistance-switching layer.