Abstract: The present disclosure relates a metal-insulator-metal (MIM) capacitor. In some embodiments, the MIM capacitor has a capacitor bottom metal (CBM) electrode arranged over a semiconductor substrate. The MIM capacitor has a high-k dielectric disposed over the CBM electrode and a capacitor top metal (CTM) electrode arranged over the high-k dielectric layer. The MIM capacitor has a dummy structure that is disposed vertically over the high-k dielectric layer and laterally apart from the CTM electrode. The dummy structure includes a conductive body having a same material as the CTM electrode.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first electrode over the semiconductor substrate. The first electrode has a ring-shaped cross section. The semiconductor device structure also includes a resistance-switching layer over the first electrode and a second electrode over the resistance-switching layer.

Abstract: The present disclosure relates to a MIM capacitor that includes a composite capacitor top metal (CTM) electrode and a composite capacitor bottom metal (CBM) electrode. The composite CBM electrode includes a first diffusion barrier layer overlying a first metal layer, and the composite CTM electrode includes a second diffusion barrier layer overlying a second metal layer. A dielectric layer is arranged over the composite CBM electrode, underlying the composite CTM electrode. The first and second diffusion barrier layers protect the first and second metal layers from metal that diffuses or moves from a metal line underlying the MIM capacitor to the composite CTM and CBM electrodes during manufacture. A method of manufacturing the MIM capacitor is also provided.

Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.

Abstract: A method of forming and a magnetoresistive random access memory (MRAM) device. In an embodiment, the MRAM device includes a magnetic tunnel junction (MTJ) disposed over a bottom electrode, the magnetic tunnel junction having a first sidewall, a top electrode disposed over the magnetic tunnel junction, and a dielectric spacer supported by the magnetic tunnel junction and extending along sidewalls of the top electrode, the dielectric spacer having a second sidewall substantially co-planar with the first sidewall of the magnetic tunnel junction.

Abstract: A manufacture includes a first electrode having an upper surface, a second electrode having a lower surface directly over the upper surface of the first electrode, a resistance variable film between the first electrode and the second electrode, and a first conductive member on and surrounding an upper portion of the second electrode.

Abstract: A phase change memory (PCM) cell with a heating element electrically isolated from laterally surrounding regions of the PCM cell by a cavity is provided. A dielectric region is arranged between first and second conductors. A heating plug is arranged within a hole extending through the dielectric region to the first conductor. The heating plug includes a heating element running along sidewalls of the hole, and includes a sidewall structure including a cavity arranged between the heating element and the sidewalls. A phase change element is in thermal communication with the heating plug and arranged between the heating plug and the second conductor. Also provide is a method for manufacturing the PCM cell.

Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.

Abstract: Some embodiments relate to a metal-insulator-metal (MIM) capacitor, which includes a capacitor a capacitor bottom metal (CBM) electrode, a high k dielectric layer arranged over the CBM electrode, and a capacitor top metal (CTM) electrode arranged over the high k dielectric layer. In some embodiments, the MIM capacitor comprises CTM protective sidewall regions, which extend along vertical sidewall surfaces of the CTM electrode, and protect the CTM electrode from leakage, premature voltage breakdown, or burn out, due to metallic residue or etch damage formed on the sidewalls during one or more etch process(es) used to form the CTM electrode. In some embodiments, the MIM capacitor comprises CBM protective sidewall regions, which extend along vertical sidewall surfaces of the CBM electrode. In some embodiments, the MIM capacitor comprises both CBM and CTM protective sidewall regions.

Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.

Abstract: Some embodiments relate to a metal-insulator-metal (MIM) capacitor, which includes a capacitor a capacitor bottom metal (CBM) electrode, a high k dielectric layer arranged over the CBM electrode, and a capacitor top metal (CTM) electrode arranged over the high k dielectric layer. In some embodiments, the MIM capacitor comprises CTM protective sidewall regions, which extend along vertical sidewall surfaces of the CTM electrode, and protect the CTM electrode from leakage, premature voltage breakdown, or burn out, due to metallic residue or etch damage formed on the sidewalls during one or more etch process(es) used to form the CTM electrode. In some embodiments, the MIM capacitor comprises CBM protective sidewall regions, which extend along vertical sidewall surfaces of the CBM electrode. In some embodiments, the MIM capacitor comprises both CBM and CTM protective sidewall regions.

Abstract: A method of forming and a magnetoresistive random access memory (MRAM) device. In an embodiment, the MRAM device includes a magnetic tunnel junction (MTJ) disposed over a bottom electrode, the magnetic tunnel junction having a first sidewall, a top electrode disposed over the magnetic tunnel junction, and a dielectric spacer supported by the magnetic tunnel junction and extending along sidewalls of the top electrode, the dielectric spacer having a second sidewall substantially co-planar with the first sidewall of the magnetic tunnel junction.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) cell having a bottom electrode that provides for efficient switching of the RRAM cell, and an associated method of formation. In some embodiments, the RRAM cell has a bottom electrode surrounded by a spacer and a bottom dielectric layer. The bottom electrode, the spacer, and the bottom dielectric layer are disposed over a lower metal interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A dielectric data storage layer having a variable resistance is located above the bottom dielectric layer and the bottom electrode, and a top electrode is disposed over the dielectric data storage layer. Placement of the spacer narrows the later formed bottom electrode, thereby improving switch efficiency of the RRAM cell.

Abstract: A device includes creating an opening in a dielectric layer that is disposed over a bottom electrode layer. A top electrode layer is disposed over the dielectric layer. A magnetic tunnel junction (MTJ) layer is formed in the opening over the bottom electrode layer.

Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.

Abstract: A method of forming and a magnetoresistive random access memory (MRAM) device. In an embodiment, the MRAM device includes a magnetic tunnel junction (MTJ) disposed over a bottom electrode, the magnetic tunnel junction having a first sidewall, a top electrode disposed over the magnetic tunnel junction, and a dielectric spacer supported by the magnetic tunnel junction and extending along sidewalls of the top electrode, the dielectric spacer having a second sidewall substantially co-planar with the first sidewall of the magnetic tunnel junction.

Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device, a method of forming a magnetic tunnel junction (MTJ) device, and a process tool. An embodiment is a process tool comprising an ion beam etch (IBE) chamber, an encapsulation chamber, a transfer module interconnecting the IBE chamber and the encapsulation chamber, the transfer module being capable of transferring a workpiece from the IBE chamber to the encapsulation chamber without exposing the workpiece to an external environment.

Abstract: A method includes creating an opening in a dielectric layer that is disposed over a bottom electrode layer. A top electrode layer is disposed over the dielectric layer. A magnetic tunnel junction (MTJ) layer is formed in the opening over the bottom electrode layer.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.

Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.