Abstract: Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a plurality of dielectric layers and a plurality of metal layers that are stacked over one another in alternating fashion. The plurality of metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ and is in direct electrical contact with a lower surface of the upper metal layer.

Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.

Abstract: A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.

Abstract: A method for fabricating a semiconductor memory device is provided. The method includes: etching a first region of the semiconductor memory device to expose a first capping layer; forming a second capping layer on the first capping layer; etching a portion of the first capping layer and a portion of the second capping layer to form a first trench reaching a first metal line; and forming a second metal line in the first trench to contact the first metal line.

Abstract: A storage device includes a first electrode, a stacked feature, a spacer and a barrier structure. The stacked feature is position over the first electrode, and includes a storage element and a second electrode over the storage element. The spacer is positioned on a sidewall of the stacked feature, the spacer having a notch positioned on a top surface of the spacer, in which the notch of the spacer has a surface which is continuous with a top surface of the stacked feature. The barrier structure is embedded in a lateral of the spacer. The barrier structure has a top extending upwards past a bottom of the notch.

Abstract: A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad.

Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor. The capacitor includes a first electrode over at least one dielectric layer over the active region. The first electrode surrounds an open space within the capacitor. The first electrode has a non-linear first electrode sidewall.

Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a bottom electrode having a first width and a dielectric structure having a second width formed over the bottom electrode. The semiconductor structure further includes a top electrode having a third width formed over the dielectric structure. In addition, the second width of the dielectric structure is greater than the first width of the bottom electrode.

Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and an (N+M)th metal layer over the Nth metal layer. N and M are positive integers. The (N+M)th metal layer surrounds a portion of a sidewall of the top electrode. A manufacturing method of forming the semiconductor structure is also provided.

Abstract: A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.

Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor having a first electrode layer, a second electrode layer, and an insulating layer between the first electrode layer and the second electrode layer. At least three dielectric layers are between a bottom surface of the capacitor and the active region.

Abstract: The present disclosure provides a semiconductor structure, including providing a metal layer, an adhesion-enhancing layer over the metal layer, a dielectric stack over the adhesion-enhancing layer, a contact penetrating the dielectric stack and the adhesion-enhancing layer and connecting with the metal layer, a barrier layer disposed between the contact and the dielectric stack, and a high-k dielectric layer disposed between the contact and the barrier layer.

Abstract: A semiconductor device includes a capacitive device, a first conductive via, and a second conductive via. The capacitive device includes a first conductive plate, a first insulating plate, a second conductive plate, a second insulating plate, and a third conductive plate. The first conductive via is electrically coupled to the first conductive plate and the third conductive plate, and the first conductive via penetrated through a first film stack with a first thickness. The second conductive via is electrically coupled to the second conductive plate, and the second conductive via penetrated through a second film stack with a second thickness. The second thickness is substantially equal to the first thickness.

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes (1) providing a substrate, (2) depositing a first electrode layer over the substrate, (3) depositing a magnetic tunneling junction (MTJ) layer on the first electrode layer, (4) depositing a second electrode layer on the MTJ layer, (5) patterning the first electrode layer, the MTJ layer and the second electrode layer to form a first electrode, an MTJ and a second electrode, (6) forming a first dielectric layer over the first electrode, the MTJ, and the second electrode, (7) removing a portion of the first dielectric layer, (8) forming a second dielectric layer over the first electrode, the MTJ, the second electrode, and an unremoved portion of the first dielectric layer. A semiconductor structure is also disclosed.

Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.

Abstract: A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.

Abstract: A magnetoresistive random access memory (MRAM) structure includes a bottom electrode structure. A magnetic tunnel junction (MTJ) element is over the bottom electrode structure. The MTJ element includes an anti-ferromagnetic material layer. A ferromagnetic pinned layer is over the anti-ferromagnetic material layer. A tunneling layer is over the ferromagnetic pinned layer. A ferromagnetic free layer is over the tunneling layer. The ferromagnetic free layer has a first portion and a demagnetized second portion. The MRAM also includes a top electrode structure over the first portion.

Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer over a transistor region, where N is a natural number, and a bottom electrode over the Nth metal layer. The bottom electrode comprises a bottom portion having a first width, disposed in a bottom electrode via (BEVA), the first width being measured at a top surface of the BEVA, and an upper portion having a second width, disposed over the bottom portion. The semiconductor structure also includes a magnetic tunneling junction (MTJ) layer having a third width, disposed over the upper portion, a top electrode over the MTJ layer and an (N+1)th metal layer over the top electrode. The first width is greater than the third width.

Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor having a first electrode layer, a second electrode layer, and an insulating layer between the first electrode layer and the second electrode layer. At least three dielectric layers are between a bottom surface of the capacitor and the active region.