Patents by Inventor Chi Chang
Chi Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240114695Abstract: Apparatuses, memory systems, capacitor structures, and techniques related to anti-ferroelectric capacitors having a cerium oxide doped hafnium zirconium oxide based anti-ferroelectric are described. A capacitor includes layers of hafnium oxide, cerium oxide, and zirconium oxide between metal electrodes. The cerium of the cerium oxide provides a mid gap state to protect the hafnium zirconium oxide during operation.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Sou-Chi Chang, Nazila Haratipour, Christopher Neumann, Shriram Shivaraman, Brian Doyle, Sarah Atanasov, Bernal Granados Alpizar, Uygar Avci
-
Publication number: 20240112714Abstract: A memory device includes a group of ferroelectric capacitors with a shared plate that extends through the ferroelectric capacitors, has a greatest width between ferroelectric capacitors, and is coupled to an access transistor. The shared plate may be vertically between ferroelectric layers of the ferroelectric capacitors at the shared plate's greatest width. The memory device may include an integrated circuit die and be coupled to a power supply. Forming a group of ferroelectric capacitors includes forming an opening through an alternating stack of insulators and conductive plates, selectively forming ferroelectric material on the conductive plates rather than the insulators, and forming a shared plate in the opening over the ferroelectric material.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Nazila Haratipour, Christopher Neumann, Brian Doyle, Sou-Chi Chang, Bernal Granados Alpizar, Sarah Atanasov, Matthew Metz, Uygar Avci, Jack Kavalieros, Shriram Shivaraman
-
Publication number: 20240114694Abstract: Backside integrated circuit capacitor structures. In an example, a capacitor structure includes a layer of ferroelectric material between first and second electrodes. The first electrode can be connected to a transistor terminal by a backside contact that extends downward from a bottom surface of the transistor terminal to the first electrode. The transistor terminal can be, for instance, a source or drain region, and the backside contact can be self-aligned with the source or drain region. The second electrode can be connected to a backside interconnect feature. In some cases, the capacitor has a height that extends through at least one backside interconnect layer. In some cases, the capacitor is a multi-plate capacitor in which the second conductor is one of a plurality of plate line conductors arranged in a staircase structure. The capacitor structure may be, for example, part of a non-volatile memory device or the cache of a processor.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Sourav Dutta, Nazila Haratipour, Uygar E. Avci, Vachan Kumar, Christopher M. Neumann, Shriram Shivaraman, Sou-Chi Chang, Brian S. Doyle
-
Publication number: 20240112731Abstract: Techniques and mechanisms for operating a ferroelectric (FE) circuit element as a cell of a crossbar memory array. In an embodiment, the crossbar memory array comprises a bit line, a word line, and a data storage cell which includes a circuit element that extends to each of the bit line and the word line. The data storage cell is a FE circuit element which comprises terminals, each at a different respective one of the bit line or the word line, and one or more material layers between said terminals. One such layer comprises a FE nitride or a FE oxide. The FE circuit element is operable to selectively enable, or disable, operation as a diode. In another embodiment, the memory array is coupled to circuitry which corresponds a given mode of operation of the FE circuit element to a particular data bit value.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Sou-Chi Chang, Chia-Ching Lin, Saima Siddiqui, Sarah Atanasov, Bernal Granados Alpizar, Uygar Avci
-
Publication number: 20240113123Abstract: An apparatus is provided which comprises: a plurality of logic blocks comprising transistors on a substrate, the logic blocks to implement logic functions; a plurality of input/output (I/O) blocks connecting the logic blocks with components external to the apparatus; a plurality of interconnect layers comprising wires and vias surrounded by interlayer dielectric above the substrate, the wires and vias conductively coupling the plurality of logic blocks and the plurality of I/O blocks; a plurality of programmable switches to configure connections between the plurality of logic blocks and the plurality of I/O blocks; and a ferroelectric material in a capacitor coupled to the gate or on the gate dielectric itself of one or more of the transistors. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Elijah V. Karpov, Sou-Chi Chang
-
Publication number: 20240114693Abstract: In one embodiment, an apparatus includes a first metal layer, a second metal layer above the first metal layer, a first metal via generally perpendicular with and connected to the first metal layer, a second metal via generally perpendicular with and connected to the second metal layer, a third metal via generally perpendicular with and extending through the first metal layer and the second metal layer, a ferroelectric material between the third metal via and the first metal layer and between the third metal via and the second metal layer, and a hard mask material around a portion of the first metal via above the first metal layer and the second metal layer, around a portion of the second metal via above the first metal layer and the second metal layer, and around a portion of the ferroelectric material above the first metal layer and the second metal layer.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Christopher M. Neumann, Brian Doyle, Nazila Haratipour, Shriram Shivaraman, Sou-Chi Chang, Uygar E. Avci, Eungnak Han, Manish Chandhok, Nafees Aminul Kabir, Gurpreet Singh
-
Publication number: 20240112730Abstract: Techniques and mechanisms for storing data with a memory cell which comprises a ferroelectric (FE) resistive junction. In an embodiment, a memory cell comprises a transistor and a FE resistive junction structure which is coupled to the transistor. The FE resistive junction structure comprises electrode structures, and a layer of a material which is between said electrode structures, wherein the material is a FE oxide or a FE semiconductor. The FE resistive junction structure selectively provides any of various levels of resistance, each to represent a respective one or more bits. A current flow through the FE resistive junction structure is characterized by thermionic emission through a Schottky barrier at an interface with one of the electrode structures. In another embodiment, the FE resistive junction structure further comprises one or more dielectric layers each between the layer of material and a different respective one of the electrode structures.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Sou-Chi Chang, Nazila Haratipour, Saima Siddiqui, Uygar Avci, Chia-Ching Lin
-
Patent number: 11948981Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming epitaxial source/drain regions on opposite sides of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, and depositing a work-function layer over the gate dielectric layer. The work-function layer comprises a seam therein. A silicon-containing layer is deposited to fill the seam. A planarization process is performed to remove excess portions of the silicon-containing layer, the work-function layer, and the gate dielectric layer. Remaining portions of the silicon-containing layer, the work-function layer, and the gate dielectric layer form a gate stack.Type: GrantFiled: August 18, 2021Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Yi Lee, Weng Chang, Chi On Chui
-
Patent number: 11947204Abstract: A cholesterol liquid crystal display device includes a liquid crystal display panel and a liquid crystal driving unit. The liquid crystal display panel has a plurality of pixels. The liquid crystal driving unit applies row driving voltages and column driving voltages to a designated pixel according to the input signal. After the input signal is transmitted, the liquid crystal driving unit activates the power-down signal within a certain period of time to reduce the row driving voltage and the column driving voltage applied to the specified pixel. Thereby, the crosstalk phenomenon on the cholesteric liquid crystal display device can be improved.Type: GrantFiled: November 14, 2022Date of Patent: April 2, 2024Assignee: IRIS OPTRONICS CO., LTD.Inventors: Wu-Chang Yang, Chi-Chang Liao
-
Patent number: 11948800Abstract: A device includes a pair of gate spacers on a substrate, and a gate structure on the substrate and between the gate spacers. The gate structure includes an interfacial layer, a metal oxide layer, a nitride-containing layer, a tungsten-containing layer, and a metal compound layer. The interfacial layer is over the substrate. The metal oxide layer is over the interfacial layer. The nitride-containing layer is over the metal oxide layer. The tungsten-containing layer is over the nitride-containing layer. The metal compound layer is over the tungsten-containing layer. The metal compound layer has a different material than a material of the tungsten-containing layer.Type: GrantFiled: December 14, 2022Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Yu Chen, Yu-Chi Lu, Chih-Pin Tsao, Shih-Hsun Chang
-
Patent number: 11948879Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first dielectric material disposed over the device, and an opening is formed in the first dielectric material. The semiconductor device structure further includes a conductive structure disposed in the opening, and the conductive structure includes a first sidewall. The semiconductor device structure further includes a surrounding structure disposed in the opening, and the surrounding structure surrounds the first sidewall of the conductive structure. The surrounding structure includes a first spacer layer and a second spacer layer adjacent the first spacer layer. The first spacer layer is separated from the second spacer layer by an air gap.Type: GrantFiled: July 27, 2022Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
-
Patent number: 11946569Abstract: An actuating and sensing module is disclosed and includes a bottom plate, a gas pressure sensor, a thin gas transportation device and a cover plate. The bottom plate includes a pressure relief orifice, a discharging orifice and a communication orifice. The gas pressure sensor is disposed on the bottom plate and seals the communication orifice. The thin gas transportation device is disposed on the bottom plate and seals the pressure relief orifice and the discharging orifice. The cover plate is disposed on the bottom plate and covers the gas pressure sensor and the thin gas-transportation device. The cover plate includes an intake orifice. The thin gas transportation device is driven to inhale gas through the intake orifice, the gas is then discharged through the discharging orifice by the thin gas transportation device, and a pressure change of the gas is sensed by the gas pressure sensor.Type: GrantFiled: April 19, 2021Date of Patent: April 2, 2024Assignee: MICROJET TECHNOLOGY CO., LTD.Inventors: Hao-Jan Mou, Shih-Chang Chen, Jia-Yu Liao, Hung-Hsin Liao, Chung-Wei Kao, Chi-Feng Huang, Yung-Lung Han, Chang-Yen Tsai, Wei-Ming Lee
-
Patent number: 11948528Abstract: The present invention relates to a driving method of a cholesteric liquid crystal display. It includes the steps in the following: driving each scan line by a dynamic driving scheme (DDS) including an Evolution phase; refreshing a frame of the cholesteric liquid crystal display by a full refresh mode, each scan line driven N times during the Evolution phase in the full refresh mode; and refreshing a part of the frame by a partial-refresh mode, each scan line driven M times in the Evolution phase in the partial-refresh mode, wherein M is greater than N.Type: GrantFiled: May 10, 2023Date of Patent: April 2, 2024Assignee: IRIS OPTRONICS CO., LTD.Inventors: Ming-Liang Tsai, Wu-Chang Yang, Chi-Chang Liao
-
Publication number: 20240103571Abstract: A portable computer includes a computer body and a handle. The handle, operable to be located at a closed position and an open position relative to the computer body, includes a body component for holding of a user, a movable member and an auxiliary member. One end of the movable member is pivotally connected to the body component and the other end is pivotally connected to the computer body. The auxiliary member is disposed on one end of the body component, and is abutted against one side of the movable member. During a movement process of the handle between the closed position and the open position, at least a portion of the movable member is kept in contact with the auxiliary member. When the handle is at the closed position and the open position, the auxiliary member and the body component jointly secure the movable member.Type: ApplicationFiled: December 5, 2023Publication date: March 28, 2024Inventors: Wan-Lin HSU, Juei-Chi CHANG
-
Publication number: 20240102194Abstract: A plating system and a method thereof are disclosed. The plating system performs a N-stage plating drilling filling process in which a M-th stage plating drilling filling process with a M-th current density is performed on a hole of a substrate for a M-th plating time to form a M-th plating layer on the to-be-plated layer, wherein N is a positive integer equal to or greater than 3, and M is a positive integer positive integer in a range of 1 to N. Therefore, the technical effect of providing a higher drilling filling rate than conventional plating filling technology under a condition that a total thickness of plating layers is fixed can be achieved.Type: ApplicationFiled: August 7, 2023Publication date: March 28, 2024Inventors: Cheng-EN HO, Yu-Lian CHEN, Cheng-Chi WANG, Yu-Jen CHANG, Yung-Sheng LU, Cheng-Yu LEE, Yu-Ming LIN
-
Publication number: 20240106159Abstract: An electronic device includes a casing and an electronic assembly. The casing has an opening between a first side surface and a second side surface parallel to each other, and the opening has a first side edge and a second side edge opposite to each other. The electronic assembly is assembled in the casing, and includes a body, a connecting portion, and a waterproof ring. The connecting portion is arranged on one side of the body. The waterproof ring includes an outer ring, an inner ring, and two blocking portions. The outer ring is a closed ring, and is arranged around an outer surface of the connecting portion. The inner ring is arranged on the outer surface of the connecting portion and is closer to the body than the outer ring. The two blocking portions are each connected to the outer ring and the inner ring.Type: ApplicationFiled: April 18, 2023Publication date: March 28, 2024Inventors: Kuang-Yeh Chang, Juei-Chi Chang
-
Publication number: 20240105400Abstract: A computing device can include a housing defining an opening, a base layer, and a button mechanism positioned in the opening. The button mechanism can include a keycap movable relative to the base layer between an undepressed state and a depressed state, and a dome contacting the keycap, the dome including a first surface and a second surface, opposite the first surface. In the undepressed state, the first surface can be concave and the second surface can be convex. In a partially depressed state, a first portion of the first surface can be convex and a second portion of the first surface can be concave. In the depressed state, the first surface can be convex and the second surface can be concave.Type: ApplicationFiled: September 22, 2022Publication date: March 28, 2024Inventors: Yu-Po Chang, Chia Chi Wu
-
Publication number: 20240107700Abstract: An electronic device includes a casing, a concave portion, and an air outlet portion. The casing includes a first side surface, a second side surface, and a third side surface that are adjacent to each other, where two sides of the first side surface are respectively connected to the second side surface and the third side surface. The concave portion is recessed at a junction of the first side surface and the second side surface and includes a first concave surface and a second concave surface. The second side surface, the first concave surface, the second concave surface, and the first side surface are sequentially connected. The air outlet portion is arranged on the first concave surface. A length of the air outlet portion in one direction is greater than a half of a length between the second side surface and the third side surface in the direction.Type: ApplicationFiled: May 4, 2023Publication date: March 28, 2024Inventors: Kuang-Yeh Chang, Juei-Chi Chang
-
Patent number: 11941610Abstract: The present disclosure provides a cryptocurrency securing system and a cryptocurrency securing method thereof. The system receives a cryptocurrency transaction information from a user device, and determines whether a policy data corresponding to the cryptocurrency transaction information is legal. When the policy data corresponding to the cryptocurrency transaction information is legal, the system derives a cryptocurrency private key information via a personal identification number of the user device. The system then encrypts the cryptocurrency transaction information via the cryptocurrency private key information for deriving an encrypted cryptocurrency transaction information, and broadcasts the encrypted cryptocurrency transaction information to a blockchain network.Type: GrantFiled: July 12, 2019Date of Patent: March 26, 2024Assignee: CIRCLE INTERNET FINANCIAL, LTDInventors: Chi-Huang Fan, Chien-Yang Hsu, Ming-Chang Shih
-
Patent number: 11940854Abstract: A replacement device includes a replacement module and a slider. The replacement module includes a sliding portion. The sliding portion is provided with a limiting column, which is formed with a fixing hole. The slider includes a slider body. The slider body is provided with a first latch, a limiting hole and a fixing element, wherein the first latch is arranged on a first side edge of the slider body. The slider is correspondingly arranged on the sliding portion of the replacement module, and the limiting column of the sliding portion passes through the limiting hole. The fixing element has a top portion, and is fixed in the fixing hole. The size of the top portion is greater than the size of the limiting hole, so that the slider moves relative to the replacement module within a limit range of the limiting hole.Type: GrantFiled: November 4, 2022Date of Patent: March 26, 2024Assignee: GETAC TECHNOLOGY CORPORATIONInventors: Hsin-Chih Chou, Wan-Lin Hsu, Juei-Chi Chang