Abstract: An apparatus includes a first platen configured to hold a first workpiece; a first dressing board; and blade holder including arms extending from a central axis, wherein the blade holder is configured to hold a blade at an end of each respective arm, wherein the blade holder is operable to rotate around the central axis, wherein the blade holder is configured to trim the first workpiece using at least one blade, wherein the blade holder is configured to dress at least one blade on the first dressing board.

Abstract: A device includes a substrate, a first fin, a second fin, a first isolation structure, a second isolation structure, and a gate structure. The first fin extends from a p-type region of the substrate. The second fin extends from an n-type region of the substrate. The first isolation structure is over the p-type region and adjacent to the first fin. The first isolation structure has a bottom surface and opposite first and second sidewalls connected to the bottom surface, a first round corner is between the bottom surface and the first sidewall of the first isolation structure, and the first sidewall is substantially parallel to the second sidewall. The second isolation structure is over the n-type region and adjacent to the first fin. The first isolation structure is deeper than the second isolation structure. The gate structure is over the first isolation structure and covering the first fin.

Abstract: An electrical connector, wherein the electrical connector can offer sufficient wiring space for the accompanying conductive cables, thereby reducing the stacking height of the conductive cables during wiring to ensure that the electrical connector and its accompanying conductive cables occupy internal space within electronic devices at expected height dimensions. Additionally, the provided electrical connector can guide the conductive cables to extend outward laterally, enabling the conductive cables to extend laterally within electronic devices to facilitate the organization of conductive cables within electronic devices and even helps avoid unnecessary tangling of conductive cables within electronic devices, allowing electronic devices to continue advancing towards thinner designs.

Abstract: A clock gating circuit includes an input circuit, a cross-coupled pair of transistors, a first transistor of a first type and a first pull-up transistor of the first type. The input circuit is configured to set a first control signal of a first node in response to a first or second enable signal. The cross-coupled pair of transistors is coupled between the first node and an output node. The first transistor is coupled between the first and a second node. The first pull-up transistor includes a first gate terminal, a first drain terminal and a first source terminal. The first gate terminal is configured to receive an inverted clock input signal. The first drain terminal is coupled to the second node and the first transistor. The first pull-up transistor is configured to adjust a clock output signal responsive to the inverted clock input signal.

Abstract: During a front side process of a wafer, a hard mask layer is formed under a metal portion of a semiconductor device, and an epitaxial layer is deposited to form epitaxial portions of the semiconductor device. In a back side process of the wafer to cut the epitaxial layer, the metal portion is covered and protected by the hard mask layer from damages during etching of the epitaxial layer.

Abstract: The embodiments of the disclosure provide a patterning method, which includes the following processes. A target layer is formed on a substrate. A hard mask layer is formed over the target layer. A first patterning process is performed on the hard mask layer by using a photomask having a first pattern with a first pitch. The photomask is shifted along a first direction by a first distance. A second patterning process is performed on the hard mask layer by using the photomask that has been shifted, so as to form a patterned hard mask. The target layer is patterned using the patterned hard mask to form a patterned target layer. The target layer has a second pattern with a second pitch less than the first pitch.

Abstract: A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first processing element, a first I/O element, a second processing element, and a second I/O element. The first processing element is on a substrate. The first I/O element is on the substrate and electrically connected to the first processing element. The second processing element is on the substrate. The second I/O element is on the substrate and electrically connected to the second processing element. The first I/O element is electrically connected to and physically separated from the second I/O element.

Abstract: A fingerprint sensing device has a sensing area, an operation area, and a peripheral area, and the operation area is disposed between the sensing area and the peripheral area. The fingerprint sensing device includes a substrate, a sensing element located at the sensing area, an operation element located at the operation area, a first signal line located at the peripheral area, a first planarization layer, a first insulating layer, and a first shading layer. The first planarization layer is located on the substrate and has a first trench, and the first trench overlaps the first signal line. The first insulating layer is located on the first planarization layer and in the first trench, and the first insulating layer has a first opening located in the first trench. The first shading layer is located on the first insulating layer and connected to the first signal line through the first opening.

Abstract: Apparatuses of reusable incontinence underwear and methods for manufacturing the same are provided. In one embodiment, an incontinence underwear includes an interior layer includes an excretion area, where the excretion area includes one or more openings configured to drain excretions of a user away from the interior layer; a middle layer configured to house an excretion collection unit, where the excretion collection unit is configured to store the urine from the interior layer to a urine collection bag external to the incontinence underwear; an exterior layer configured to conceal and prevent leakage from the middle layer of the incontinence underwear; and a support frame configured to hold the interior layer, the middle layer and the exterior layer of the incontinence underwear together.

Abstract: An optical element driving mechanism is provided in the present disclosure, including a fixed portion, a first movable portion, and a driving assembly. The first movable portion is movable relative to the fixed portion. The driving assembly drives the first movable portion to move relative to the fixed portion. The first movable portion brings an optical element to move.

Abstract: An optical coherence tomography image system and an autofocus method thereof are provided. The autofocus method captures a reference chart at a plurality of preset diopter positions, receives an interference signal generated by the reflection of a light beam projected onto an eyeball, and analyzes the reference chart and the interference signal to obtain an analysis value and a corresponding diopter. The method compares the plurality of analysis values to obtain one meeting the standard condition as the target analysis value. According to the target analysis value and the corresponding diopter, the focusing driving device is controlled to move to the position corresponding to the diopter to complete autofocusing. Therefore, the present invention can reduce the time of autofocusing, obtain a higher shooting success rate, provide better user experience, and use a lower-order computing device to reduce costs.

Abstract: A multimedia device comprises a power input interface, a computing circuit and a load circuit. The power input interface is configured to receive an operating voltage. The computing circuit is configured to receive the operating voltage from the power input interface, and configured to output a pulse-width modulation (PWM) signal. The load circuit is configured to receive a test current from the power input interface, receive the PWM signal, and determine a magnitude of the test current according to a duty ratio of the PWM signal. The computing circuit is configured to monitor the variation of the operating voltage while adjusting the duty ratio of the PWM signal step by step. The computing circuit is configured to determine an upper bound of a power consumption of the computing circuit according to the relationship between the operating voltage and the duty ratio of the PWM signal.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a first trench over a first portion of the substrate and a second trench over a second portion of the substrate. The method includes forming a first work function layer in the first trench and the second trench. The method includes forming a first mask layer over the first work function layer in the first trench. The method includes removing the first work function layer exposed by the first mask layer. The method includes removing the first mask layer. The method includes forming a first gate electrode in the first trench and a second gate electrode in the second trench. The method includes forming a first hard mask layer in the first trench and a second hard mask layer in the second trench.

Abstract: A semiconductor device includes a substrate, a gate oxide layer formed on the substrate, a gate formed on the gate oxide layer, and a spacer formed adjacent the gate and over the substrate. The spacer includes a void filled with air to prevent leakage of charge to and from the gate, thereby reducing data loss and providing better memory retention. The reduction in charge leakage results from reduced parasitic capacitances, fringing capacitances, and overlap capacitances due to the low dielectric constant of air relative to other spacer materials. The spacer can include multiple layers such as oxide and nitride layers. In some embodiments, the semiconductor device is a multiple-time programmable (MTP) memory device.

Abstract: A static random access memory (SRAM) cell includes a first pull-up (PU) transistor comprising a first gate structure. The SRAM cell further includes a second PU transistor comprising a second gate structure, wherein the second gate structure comprises a gate stack and gate spacers. The SRAM cell further includes a first butted contact, wherein the first butted contact electrically connects a first terminal of the first PU transistor to the second gate structure, wherein the first butted contact directly contacts each of a top surface and a sidewall of the gate stack.

Abstract: A semiconductor device and a method for forming the same are provided. The semiconductor device includes a substrate and a gate structure. The gate structure is disposed in the substrate and includes a shielded gate, a control gate, and a plurality of insulating layers. The shielded gate includes a bottom gate and a top gate. The bottom gate includes a step structure consisting of a plurality of electrodes. A width of the electrode is smaller as the electrode is farther away from the top gate, and a width of the top gate is smaller than a width of the electrode closest to the top gate. The control gate is disposed on the shielded gate. A first insulating layer is disposed between the shielded gate and the substrate. A second insulating layer is disposed on the shielded gate. A third insulating layer is disposed between the control gate and the substrate.

Abstract: A holographic calling system can capture and encode holographic data at a sender-side of a holographic calling pipeline and decode and present the holographic data as a 3D representation of a sender at a receiver-side of the holographic calling pipeline. The holographic calling pipeline can include stages to capture audio, color images, and depth images; densify the depth images to have a depth value for each pixel while generating parts masks and a body model; use the masks to segment the images into parts needed for hologram generation; convert depth images into a 3D mesh; paint the 3D mesh with color data; perform torso disocclusion; perform face reconstruction; and perform audio synchronization. In various implementations, different of these stages can be performed sender-side or receiver side. The holographic calling pipeline also includes sender-side compression, transmission over a communication channel, and receiver-side decompression and hologram output.

Abstract: Disclosed herein is an isolated strain of Roseburia hominis HGM001, which is deposited at Deutsche Sammlung von Mikroorganismen and Zellkulturen GmbH under an accession number DSM 34119. A method for producing butyric acid using the isolated strain of Roseburia hominis HGM001, a fermented culture produced by the method, and a method for alleviating an inflammatory disorder using the fermented culture are also disclosed.

Abstract: A metal-oxide semiconductor field-effect transistor with asymmetric parallel dies and a method of using the same, including an inductor, a load recognition control unit and a metal-oxide semiconductor field-effect transistor having a first die, a second die, and a switch. The first die is larger in size than the second die. The inductor produces a voltage signal when the load changes. The switch is controlled by the load recognition control unit such that different dies are switched on under different load conditions, thereby improving efficiency under light load condition in addition to reducing volume and cost.