Patents by Inventor Chi Chen
Chi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240152679Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.Type: ApplicationFiled: January 17, 2024Publication date: May 9, 2024Inventors: Rachid Salik, Chin-Chang Hsu, Cheng-Chi Wu, Chien-Wen Chen, Wen-Ju Yang
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Publication number: 20240154972Abstract: A method for permission management includes: generating a plurality of job roles with different permissions according to organization permission table; generating first permission structure directed graph according to the job roles; selecting one of the job roles in first permission structure directed graph as target job role; generating minimum directed spanning graph in first permission structure directed graph according to target job role; determining whether permission of each of the job roles in first permission structure directed graph matches job of each of the job roles in first permission structure directed graph; and adjusting permission and job of each of the job roles to generate second permission structure directed graph if it is determined that permission of each of the job roles in first permission structure directed graph does not match job of each of the job roles in first permission structure directed graph.Type: ApplicationFiled: December 21, 2022Publication date: May 9, 2024Inventors: Wei-Chao CHEN, Ming-Chi CHANG, Chih-Pin WEI, Chuo-Jui WU
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Publication number: 20240153979Abstract: A method of manufacturing an image sensor structure includes forming an isolation structure in a substrate to divide the substrate into a first region and a second region, forming a first light sensing region in the first region and a second light sensing region in the second region, forming a first gate structure over the first light sensing region and a second gate structure over the second light sensing region, forming gate spacers on sidewalls of the first and second gate structures, and depositing a blocking layer on sidewalls of the gate spacers. The blocking layer has an opening positioned between the first and second gate structures. A source/drain structure is formed directly under the opening in the blocking layer. The method also includes forming an interlayer dielectric layer over the first and second gate structures and the blocking layer.Type: ApplicationFiled: April 13, 2023Publication date: May 9, 2024Inventors: Wei Long CHEN, Wen-I HSU, Feng-Chi HUNG, Jen-Cheng LIU, Dun-Nian YAUNG
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Publication number: 20240151686Abstract: A method of fabricating a semiconductor device for sensing biological material includes: forming a field-effect transistor (FET) on a semiconductor substrate that includes a gate; forming a well within a material disposed over the semiconductor substrate, the well having an opening at a first end and a floor at second end, the well further having one or more side walls extending from the floor toward the opening to define an open-ended cavity into which a fluid may be flowed; forming a via extending through the floor such that an end-most surface of the via resides proud of the floor in a direction of the well's opening, the via being electrically coupled to the gate; and forming a sensing layer that at least partially covers the floor and a portion of the via residing proud of the floor, the sensing layer being reactive to exposure to a biological material.Type: ApplicationFiled: January 4, 2023Publication date: May 9, 2024Inventors: Chuan-Chi Yan, Yueh-Chuan Lee, Chia-Chan Chen
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Publication number: 20240150567Abstract: A resin composition and the uses of it are provided. The resin composition comprises: (A) a polyfunctional vinyl aromatic copolymer; and (B) a diene compound, represented by the following formula (I) wherein, in formula (I), R10 and R11 are independently H, a C1-C6 linear or branched alkyl, with the proviso that R10 and R11 are not simultaneously H; and the polyfunctional vinyl aromatic copolymer (A) is prepared by copolymerizing one or more divinyl aromatic compounds with one or more monovinyl aromatic compounds.Type: ApplicationFiled: November 17, 2022Publication date: May 9, 2024Applicant: TAIWAN UNION TECHNOLOGY CORPORATIONInventors: JEN-CHI CHIANG, MENG-HUEI CHEN
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Patent number: 11978503Abstract: The present disclosure relates to a method and apparatus for determining a signal margin (SM) of a memory cell, a storage medium and an electronic device, and relates to the technical field of integrated circuits. The method for determining an SM of a memory cell includes: when the memory cell performs write and read operations, determining a sense signal threshold of the memory cell under an influence of a noise; and determining, based on the sense signal threshold, an actual SM of the memory cell during data reading.Type: GrantFiled: January 21, 2022Date of Patent: May 7, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Jian Chen, Chi-Shian Wu
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Patent number: 11976776Abstract: A stand adjustment device has a tripod-connecting member, a connecting seat, a proximal clamping plate, a boom-connecting tube, a locking shaft, and a manual operating member. The connecting seat is rotatably located around the tripod-connecting member. The proximal clamping plate is detachably attached to a side of the connecting seat. One end of the locking shaft is movably disposed in the boom-connecting tube. The boom is slidably mounted through the boom-connecting tube and the locking shaft. The locking shaft is slidably mounted through the boom-connecting tube, the proximal clamping plate, and the connecting seat such that the boom-connecting tube is rotatable relative to the connecting seat. The manual operating member and the locking shaft are configured to clamp the boom-connecting tube, the proximal clamping plate, and the connecting seat therebetween into a locked condition.Type: GrantFiled: May 30, 2023Date of Patent: May 7, 2024Assignee: RELIANCE INTERNATIONAL CORP.Inventors: Pei-Chi Chu, Cheng-Lin Ho, Chi-Chia Huang, Wei-Ting Chen
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Patent number: 11976124Abstract: The present disclosure provides isolated monoclonal antibodies or an antigen-binding portion thereof that specifically bind to CD40 preferably human CD40 with high affinity, and that function as CD40 agonists. The disclosed invention also relates to antibodies that are chimeric, humanized, bispecific, derivatized, single chain antibodies or portions of fusion proteins. Nucleic acid molecules encoding the antibodies of the disclosed invention, hybridoma, and methods for expressing the antibodies of the disclosed invention are also provided. Pharmaceutical compositions comprising the antibodies of the disclosed invention are also provided. This disclosure also provides methods for regulating humoral and cellular immune responses, as well as methods for treating cancer using an anti-CD40 agonist antibody of the disclosed invention.Type: GrantFiled: December 23, 2020Date of Patent: May 7, 2024Assignee: ABVISION, INC.Inventors: Chang-Hsin Chen, Gloria Zhang, Guochen Yan, Cheng-Chi Chao
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Patent number: 11978773Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a base structure. The semiconductor device structure also includes a first epitaxial structure and a second epitaxial structure sandwiching the channel structures. The semiconductor device structure further includes a gate stack wrapped around each of the channel structures and a backside conductive contact connected to the second epitaxial structure. A first portion of the backside conductive contact is directly below the base structure, and a second portion of the backside conductive contact extends upwards to approach a bottom surface of the second epitaxial structure. In addition, the semiconductor device structure includes an insulating spacer between a sidewall of the base structure and the backside conductive contact.Type: GrantFiled: March 25, 2021Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Shih-Chuan Chiu, Cheng-Chi Chuang, Chih-Hao Wang
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Patent number: 11976018Abstract: Disclosed is a diamine compound represented by Formula (1), in which R1, R2, R3, R4, R5, X1, X2, X3, X4, m, n, a, b, c, and d are as defined herein. Also disclosed are a method for manufacturing the diamine compound, a composition including the diamine compound having a (chain alkoxy-methylene) phenyl group or a (hydroxyl-methylene) phenyl group, and a polymer including the (chain alkoxy-methylene) phenyl group or the (hydroxyl-methylene) phenyl group.Type: GrantFiled: March 9, 2021Date of Patent: May 7, 2024Assignee: DAXIN MATERIALS CORP.Inventors: Kai-Sheng Jeng, Yuan-Li Liao, You-Ming Chen, Yu-Ying Kuo, Shao-Chi Cheng
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Publication number: 20240143189Abstract: An apparatus comprises a processing device configured to maintain, for a storage system implementing a mapped redundant array of independent disks (RAID) configuration including disk groups providing RAID groups comprising data and hot spare extents, a shared pool of hot spare extents comprising first and second sets of hot spare extents from first and second ones of the disk groups. The processing device is further configured to detect failure of a disk in the first disk group, to determine whether available ones of the first set of hot spare extents provide sufficient storage capacity for rebuilding the failed disk and, responsive to determining that available ones of the first set of hot spare extents do not provide sufficient storage capacity for rebuilding the failed disk, to rebuild the failed disk utilizing one or more of the second set of hot spare extents in the shared pool of hot spare extents.Type: ApplicationFiled: November 15, 2022Publication date: May 2, 2024Inventors: Hailan Dong, Si Zhang, Chi Chen
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Publication number: 20240145245Abstract: Embodiments of the present disclosure generally relate to methods for enhancing carbon hardmask to have improved etching selectivity and profile control. In some embodiments, a method of treating a carbon hardmask layer is provided and includes positioning a workpiece within a process region of a processing chamber, where the workpiece has a carbon hardmask layer disposed on or over an underlying layer, and treating the carbon hardmask layer by exposing the workpiece to a sequential infiltration synthesis (SIS) process to produce an aluminum oxide carbon hybrid hardmask which is denser than the carbon hardmask layer. The SIS process includes exposing and infiltrating the carbon hardmask layer with an aluminum precursor, purging to remove gaseous remnants, exposing and infiltrating the carbon hardmask layer to an oxidizing agent to produce an aluminum oxide coating disposed on inner surfaces of the carbon hardmask layer, and purging the process region to remove gaseous remnants.Type: ApplicationFiled: August 24, 2023Publication date: May 2, 2024Applicant: Applied Materials, Inc.Inventors: Yung-chen LIN, Zhiyu HUANG, Chi-I LANG, Ho-yung HWANG
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Publication number: 20240145370Abstract: A semiconductor device includes a first region and a second region, and the second region surrounds the first region. The semiconductor device includes at least one electronic unit, a redistribution structure, a plurality of first pads, and a plurality of second pads. The redistribution structure may be electrically connected to at least one electronic unit. A plurality of first pads are arranged on the redistribution structure and correspondingly to the first region. There is a first pitch between two adjacent first pads. A plurality of second pads are arranged on the redistribution structure and correspondingly to the second region. There is a second pitch between two adjacent second pads, so that the first pitch is smaller than the second pitch.Type: ApplicationFiled: December 18, 2022Publication date: May 2, 2024Applicant: InnoLux CorporationInventors: Te-Hsun LIN, Wen-Hsiang LIAO, Ming-Hsien SHIH, Yung-Feng CHEN, Cheng-Chi WANG
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Publication number: 20240142301Abstract: The present disclosure provides a sensing circuit, including a photo-sensing component, a first transistor, and a temperature-sensing component. The photo-sensing component is configured to receive a light and transmit a first current according to an intensity of the light. A gate terminal of the first transistor is configured to receive a first control circuit. The photo-sensing component and the first transistor are coupled in series between first and second nodes. The temperature-sensing component is coupled between the first and second nodes and is configured to generate a second current according to a temperature. The temperature-sensing component includes a channel structure, a first gate, a second gate, and a light-shielding structure. The channel structure is configured to transmit the second current.Type: ApplicationFiled: December 14, 2022Publication date: May 2, 2024Inventors: Ming-Yao CHEN, Chang-Hung LI, Shin-Shueh CHEN, Jui-Chi LO
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Publication number: 20240142869Abstract: Embodiments of the present disclosure generally relate to methods for enhancing carbon hardmask to have improved etching selectivity and profile control. In some embodiments, a method of treating a carbon hardmask layer is provided and includes positioning a workpiece within a process region of a processing chamber, where the workpiece has a carbon hardmask layer disposed on or over an underlying layer, and treating the carbon hardmask layer by exposing the workpiece to a sequential infiltration synthesis (SIS) process to produce an aluminum oxide carbon hybrid hardmask which is denser than the carbon hardmask layer. The SIS process includes exposing and infiltrating the carbon hardmask layer with an aluminum precursor, purging to remove gaseous remnants, exposing and infiltrating the carbon hardmask layer to an oxidizing agent to produce an aluminum oxide coating disposed on inner surfaces of the carbon hardmask layer, and purging the process region to remove gaseous remnants.Type: ApplicationFiled: August 24, 2023Publication date: May 2, 2024Inventors: Yung-chen LIN, Zhiyu HUANG, Chi-I LANG, Ho-yung HWANG
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Publication number: 20240140554Abstract: Example front forks for bicycles are described herein. An example front fork includes a crown having a top side and a bottom side opposite the top side. The crown defines an opening between the top side and the bottom side. The front fork includes a first leg and a second leg coupled to and extending from the bottom side of the crown. The front fork also includes a steerer tube disposed in the opening of the crown and extending from the top side of the crown. The steerer tube and the crown coupled by a weld at or near the bottom side of the crown.Type: ApplicationFiled: October 28, 2022Publication date: May 2, 2024Applicant: SRAM, LLCInventors: CHI HUI SU, HONG CHOU LEE, CHU CHEN WANG, EN-CHIEH CHEN
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Publication number: 20240146205Abstract: A flyback power converter includes a power transformer, a first lossless voltage conversion circuit, a first low-dropout linear regulator and a secondary side power supply circuit. The first low-dropout linear regulator (LDO) generates a first operation voltage as power supply for being supplied to a sub-operation circuit. The secondary side power supply circuit includes a second lossless voltage conversion circuit and a second LDO. The second LDO generates a second operation voltage. The first operation voltage and the second operation voltage are shunted to a common node. When a first lossless conversion voltage is greater than a first threshold voltage, the second LDO is enabled to generate the second operation voltage to replace the first operation voltage as power supply supplied to the sub-operation circuit; wherein the second lossless conversion voltage is lower than the first lossless switching voltage.Type: ApplicationFiled: September 23, 2023Publication date: May 2, 2024Inventors: Shin-Li Lin, He-Yi Shu, Shih-Jen Yang, Ta-Yung Yang, Yi-Min Shiu, Chih-Ching Lee, Yu-Chieh Hsieh, Chao-Chi Chen
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Publication number: 20240142870Abstract: Embodiments of the present disclosure generally relate to methods for enhancing carbon hardmask to have improved etching selectivity and profile control. In some embodiments, a method of treating a carbon hardmask layer is provided and includes positioning a workpiece within a process region of a processing chamber, where the workpiece has a carbon hardmask layer disposed on or over an underlying layer, and treating the carbon hardmask layer by exposing the workpiece to a sequential infiltration synthesis (SIS) process to produce an aluminum oxide carbon hybrid hardmask which is denser than the carbon hardmask layer. The SIS process includes exposing and infiltrating the carbon hardmask layer with an aluminum precursor, purging to remove gaseous remnants, exposing and infiltrating the carbon hardmask layer to an oxidizing agent to produce an aluminum oxide coating disposed on inner surfaces of the carbon hardmask layer, and purging the process region to remove gaseous remnants.Type: ApplicationFiled: August 24, 2023Publication date: May 2, 2024Applicant: Applied Materials, Inc.Inventors: Yung-chen LIN, Zhiyu HUANG, Chi-I LANG, Ho-yung HWANG
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Publication number: 20240143455Abstract: A virtual machine backup method, performed by a first host, includes: capturing a request to write data from a virtual machine to a hard disk image file, wherein the request includes written data and input and output location information, copying the written data to a temporary storage area, calculating a first key of the written data, storing the first key, the input and output location information into a first resource location structure, pausing an operation of the virtual machine and generating a second resource location structure according to the first resource location structure, the first key and a second key, and outputting a backup data set to a second host according to the second resource location structure, wherein the backup data set includes the second resource location structure and only one of existing data and the written data when the first key and the second key are the same.Type: ApplicationFiled: May 15, 2023Publication date: May 2, 2024Applicant: INSTITUTE FOR INFORMATION INDUSTRYInventors: Lee Chung CHEN, Li Hao CHIANG, Gin CHI, Wei Jie HSU, Jiann Wen WANG, Wen Dwo HWANG
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Patent number: 11971298Abstract: The present disclosure provides a sensing circuit, including a photo-sensing component, a first transistor, and a temperature-sensing component. The photo-sensing component is configured to receive a light and transmit a first current according to an intensity of the light. A gate terminal of the first transistor is configured to receive a first control circuit. The photo-sensing component and the first transistor are coupled in series between first and second nodes. The temperature-sensing component is coupled between the first and second nodes and is configured to generate a second current according to a temperature. The temperature-sensing component includes a channel structure, a first gate, a second gate, and a light-shielding structure. The channel structure is configured to transmit the second current.Type: GrantFiled: December 14, 2022Date of Patent: April 30, 2024Assignee: AUO CORPORATIONInventors: Ming-Yao Chen, Chang-Hung Li, Shin-Shueh Chen, Jui-Chi Lo