Abstract: A laptop computer including a system host, a modular platform, a rail structure, and at least one tool is provided. The rail structure is disposed at the system host and the modular platform, and the modular platform slides relative to the system host via the rail structure to be assembled to or detached from the system host. The tool is plugged into or out of the system host, and the tool is located on a sliding path of the modular platform when the tool is assembled to the system host.

Abstract: An example device for decoding video data includes a memory configured to store video data; and one or more processors configured to: decode data representing an initial motion vector for a current block of the video data, the initial motion vector having integer-motion vector difference (MVD) precision; determine a search range around a reference area identified by the initial motion vector in a reference picture; perform a template matching search process in the search range to identify a best matching region; determine error values for neighboring pixels to the best matching region; use the error values for the neighboring pixels to perform a model-based fractional-pixel motion vector refinement to derive motion vector difference values; apply at least one of the motion vector difference values to the initial motion vector to determine a refined motion vector for the current block; and decode the current block using the refined motion vector.

Abstract: A semiconductor structure including a first dielectric layer and a conductive pattern is provided. The conductive pattern is disposed in the first dielectric layer, wherein the conductive pattern comprises an alloy layer and a first conductive layer, the alloy layer surrounds sidewalls and a bottom surface of the first conductive layer, a material of the alloy layer comprises an alloy of at least two metals, and at least one of the at least two metals relative to the rest of the at least two metals tends to be reacted with a dielectric material of the first dielectric layer.

Abstract: A fault diagnosis method applied to an optical tunnel network system (OPTUNS) having multiple optical switches and multiple optical fibers connected to the multiple optical switches is disclosed and includes following steps: detecting whether the multiple tunnels of the OPTUNS include a faulty tunnel, where each tunnel respectively passes through multiple component parts; when the faulty tunnel is detected, querying the multiple component parts that are passed through by the tunnels within a certain range with the faulty tunnel; respectively calculating a faulty count of each component part queried, where the faulty count indicates the quantity that the component parts being passed through by the faulty tunnels; and outputting one or more of the component parts that have the faulty count of non-zero.

Abstract: A projection device includes a light source module, a display panel, a freeform-surface reflective mirror, and a projection lens. The light source module includes a light source, a first Fresnel lens element, and a second Fresnel lens element. The first Fresnel lens element and the second Fresnel lens element are parallel to each other and located between the light source and the display panel. The display panel is arranged between the light source module and the freeform-surface reflective mirror. The projection lens is configured to transmit an image beam out of the projection device, and a direction of an optical axis of the projection lens is different from a direction of a normal of the first Fresnel lens element.

Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.

Abstract: An electronic package module and a method for fabrication of the same are provided. The method includes providing an electronic component assembly and a circuit substrate. The electronic component assembly includes two electronic components and a conductive structure. The electronic components are connected to each other through a conductive adhesive material, while the electronic components are connected to the conductive structure through another conductive adhesive material. A soldering material is formed on the circuit substrate, and the electronic component assembly is disposed on the soldering material. The melting points of the conductive adhesive materials are higher than the melting point of the soldering material. As a result, the conductive adhesive materials are prevented from failure during the soldering process, and thus the process yield is improved.

Abstract: Field effect transistor (FET) devices having a heterogeneous/segmented channel region and methods for fabricating the same are provided. In one example, a fin-like field effect transistor (FinFET) device includes a substrate, a fin structure disposed on the substrate, a segmented channel region formed in the fin structure, two source/drain (S/D) regions separated by the segmented channel region, and a gate structure wrapping around the segmented channel region. The segmented channel region further includes multiple channel segments sequentially arranged in the segmented channel region, and the multiple channel segments include a first channel segment and a second channel segment. The first channel segment includes a first channel barrier material dispersed therein and has a first energy barrier, and the first energy barrier is at least 0.1 electron volts (eV) in a carrier flow path between the two S/D regions when the FinFET device is not activated for operation.

Abstract: A display device, characterized in that the display device includes a first panel, having a first side and a first light shielding layer at a periphery of the first panel, wherein the first light shielding layer has a first edge departing away from the first side; and a second panel, disposed on the first panel, and having a second side adjacent to the first side; wherein the second panel includes a second light shielding layer at a periphery of the second panel; and the second light shielding layer has a second edge departing away from the second side. Wherein a first width is measured from the first side to the first edge along a direction, a second width is measured from the second side to the second edge along the direction, the second width is greater than the first width, and the direction is vertical to the first side.

Abstract: The present invention provides methods of establishing a wireless communication connection. The method includes establishing a Bluetooth low energy (BLE) connection between an electronic device and a mobile device. The electronic device transmits first connection information related to the electronic device to the mobile device using BLE. The method further includes transmitting a first Wi-Fi direct pairing request from the mobile device to the electronic device according to the first connection information. According to the method, the electronic device obtains second connection information related to the mobile device according to the first Wi-Fi direct pairing request and cancels the first Wi-Fi direct pairing request. The method further includes using the electronic device to transmit a second Wi-Fi direct pairing request to the mobile device according to the second connection information to establish a Wi-Fi direct connection.

Abstract: A method includes forming a conductive member over a first conductive line; forming a second conductive line over the conductive member; and removing a portion of the conductive member exposed by the second conductive line to form a conductive via. The formation of the second conductive line is implemented prior to the formation of the conductive via. A semiconductor structure includes a first conductive line having a first surface; a second conductive line disposed above the first conductive line and having a second surface overlapping the first surface; and a conductive via electrically connected to the first surface and the second surface. The conductive via includes a first end disposed within the first surface, a second end disposed within the second surface, and a cross-section between the first end and the second end, wherein at least two of interior angles of the cross-section are substantially unequal to 90°.

Abstract: The present disclosure describes an image sensor device and a method for forming the same. The image sensor device can include a semiconductor layer. The semiconductor layer can include a first surface and a second surface. The image sensor device can further include an interconnect structure formed over the first surface of the semiconductor layer, first and second radiation sensing regions formed in the second surface of the semiconductor layer, a metal stack formed over the second radiation sensing region, and a passivation layer formed through the metal stack and over a top surface of the first radiation sensing region. The metal stack can be between the passivation layer and an other top surface of the second radiation sensing region.

Abstract: A video decoder may be configured to receive a block of video data that was encoded using a coding mode that includes a search process in one or more reference frames. The video decoder may prefetch reference samples in a fixed search region of at least one reference frame of the one or more reference frames, and decode the block of video data using the coding mode, including performing the search process for the coding mode using the prefetched reference samples.

Abstract: A phosphine oxide group-contained transition metal complex represented by chemical formula (1), and a polymer, a mixture, a composition, and an organic electronic device.

Abstract: An integrated circuit includes a substrate at a front side of the integrated circuit. A first gate all around transistor is disposed on the substrate. The first gate all around transistor includes a channel region including at least one semiconductor nanostructure, source/drain regions arranged at opposite sides of the channel region, and a gate electrode. A shallow trench isolation region extends into the integrated circuit from the backside. A backside gate plug extends into the integrated circuit from the backside and contacts the gate electrode of the first gate all around transistor. The backside gate plug laterally contacts the shallow trench isolation region at the backside of the integrated circuit.

Abstract: A weight training sled with enhanced load effect is disclosed. The main frame has a first end and a second end remote from each other. Two first wheels, in a rotatable state, disposed at either side of the first end. A second wheel, in a rotatable state, disposed at the second end. The damping structure, disposed on the main frame and connected to the second wheel. An operating handle, erected at the first end of the main frame. An auxiliary push frame, erected at the second end of the main frame with a stand portion and a handlebar portion coupled to the upper end of the stand portion. An enhanced weight load holder, disposed on the handlebar portion, including a stop portion spaced from the handlebar portion, forming a handgrip clearance space. A weight member, placed on the enhanced weight load holder and limited in position by the stop portion.

Abstract: A data processing method applied in a data center is provided.

Abstract: Provided is a semiconductor device including: a substrate, a plurality of isolation structures, a plurality of channel layers, and a gate structure. The substrate includes a plurality of fins thereon. The plurality of isolation structures are respectively disposed between the plurality of fins. A top surface of the plurality of isolation structures is higher than a top surface of the plurality of fins to form a plurality of openings. The plurality of channel layers are respectively disposed in the plurality of openings. Each channel layer is in contact with a corresponding fin and extends to cover a lower sidewall of a corresponding isolation structure, thereby forming a U-shaped structure. The gate structure is filled in the plurality of openings and extends to cover the top surface of the plurality of isolation structures.

Abstract: The present invention relates to a phthalate free propylene-ethylene copolymer having high ethylene content characterized by low hexane extractable and xylene soluble properties, while showing excellent mechanical properties. The preparation of the copolymer is carried out in the presence of a phthalate free catalyst system comprising (a) phthalate free catalyst component obtained by contacting a magnesium halide, a titanium compound having at least a Ti-halogen bond and one or more electron donor compounds comprising urea, a carbonate ether, and a 1,3-diether; (b) an alkyl aluminum compound; and (c) an external electron donor compound.

Abstract: A method for manufacturing a semiconductor device includes: forming an etch stop layer with an opening; forming a barrier layer on the etch stop layer to fill the opening, the barrier layer including a layer portion disposed on the etch stop layer and an insert portion protruding from the layer portion to be inserted into the opening of the etch stop layer; forming a bottom electrode layer on the layer portion of the barrier layer opposite to the etch stop layer; forming a ferroelectric layer on the bottom electrode layer opposite to the barrier layer; and forming a top electrode layer on the ferroelectric layer opposite to the bottom electrode layer.