Patents by Inventor Chi Chen

Chi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240102869
    Abstract: A temperature sensing device includes a resistor string and a control circuitry. The resistor string includes a variable resistor, a first resistor, and a second resistor which are coupled in series with each other. The resistor string is coupled between a sensing end and a reference ground voltage. The first resistor and the second resistor are coupled to a monitoring end to provide a monitoring voltage. The control circuitry compares the monitoring voltage with a plurality of reference voltages to generate sensing temperature information, and generate adjustment information according to the sensing temperature information. The control circuitry adjusts a resistance provided by the variable resistor according to the adjustment information. The first resistor is a polysilicon resistor, and the second resistor is a silicon carbide diffusion resistor.
    Type: Application
    Filed: November 2, 2022
    Publication date: March 28, 2024
    Applicant: LEAP Semiconductor Corp.
    Inventors: Wei-Fan Chen, Kuo-Chi Tsai
  • Publication number: 20240106428
    Abstract: An electronic device and a temperature detection device thereof are provided. The temperature detection device includes a first resistor, a second resistor, and an operation circuit. The first resistor and the second resistor are coupled in series between a detection end and a first voltage. The first resistor and the second resistor divide a detection voltage on the detection end to generate a monitoring voltage. The operation circuit compares the monitoring voltage with a plurality of reference voltages to generate a plurality of comparison results. The operation circuit performs an operation on the comparison results to generate detection temperature information. The first resistor is a poly-silicon resistor and the second resistor is a silicon carbon (SiC) diffusion resistor.
    Type: Application
    Filed: November 28, 2022
    Publication date: March 28, 2024
    Applicant: LEAP Semiconductor Corp.
    Inventors: Wei-Fan Chen, Kuo-Chi Tsai
  • Publication number: 20240102194
    Abstract: A plating system and a method thereof are disclosed. The plating system performs a N-stage plating drilling filling process in which a M-th stage plating drilling filling process with a M-th current density is performed on a hole of a substrate for a M-th plating time to form a M-th plating layer on the to-be-plated layer, wherein N is a positive integer equal to or greater than 3, and M is a positive integer positive integer in a range of 1 to N. Therefore, the technical effect of providing a higher drilling filling rate than conventional plating filling technology under a condition that a total thickness of plating layers is fixed can be achieved.
    Type: Application
    Filed: August 7, 2023
    Publication date: March 28, 2024
    Inventors: Cheng-EN HO, Yu-Lian CHEN, Cheng-Chi WANG, Yu-Jen CHANG, Yung-Sheng LU, Cheng-Yu LEE, Yu-Ming LIN
  • Patent number: 11942547
    Abstract: The present disclosure describes a method that mitigates the formation of facets in source/drain silicon germanium (SiGe) epitaxial layers. The method includes forming an isolation region around a semiconductor layer and a gate structure partially over the semiconductor layer and the isolation region. Disposing first photoresist structures over the gate structure, a portion of the isolation region, and a portion of the semiconductor layer and doping, with germanium (Ge), exposed portions of the semiconductor layer and exposed portions of the isolation region to form Ge-doped regions that extend from the semiconductor layer to the isolation region. The method further includes disposing second photoresist structures over the isolation region and etching exposed Ge-doped regions in the semiconductor layer to form openings, where the openings include at least one common sidewall with the Ge-doped regions in the isolation region. Finally the method includes growing a SiGe epitaxial stack in the openings.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh Singh, Hsin-Chi Chen, Kun-Tsang Chuang
  • Patent number: 11941302
    Abstract: Techniques for managing disks involve determining performance information of an access pattern of a disk slice based on differences in performance parameters of the access pattern of the disk slice on a plurality of disks. Such techniques further involve determining a score for the disk slice based on the performance information and access frequency information of the disk slice. Such techniques further involve determining a position of the disk slice in the plurality of disks based on the score.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: March 26, 2024
    Assignee: Dell Products L.P.
    Inventors: Hailan Dong, Changyue Dai, Chi Chen
  • Patent number: 11942750
    Abstract: A laser inspection system is provided. A laser source emits a laser with a first spectrum and the laser is transmitted by a first optical fiber. A gain optical fiber doped with special ions is connected to the first optical fiber, and a light detector is provided around the gain optical fiber. When the laser with the first spectrum passes through the gain optical fiber, the gain optical fiber absorbs part of the energy level of the laser with the first spectrum, so that the laser with the first spectrum is converted to generate light with a second spectrum based on the frequency conversion phenomenon. The light detector detects the intensity of the light with the second spectrum, so that the power of the laser source can be obtained.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: March 26, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yi-Chi Lee, Hsin-Chia Su, Shih-Ting Lin, Yu-Cheng Song, Fu-Shun Ho, Chih-Chun Chen
  • Patent number: 11940952
    Abstract: A system for providing user access to electronic mail includes an email client and an email server. The email client receives and communicates a user interaction with an email message The email server that receives the communication, determines whether the email message stored in a live database or in a backup storage. Upon determination that the email message is stored in a backup storage, the email server performs a message exchange with a backup storage system to perform the user-requested action.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: March 26, 2024
    Assignee: Commvault Systems, Inc.
    Inventors: Arun Prasad Amarendran, Jun H. Ahn, Tirthankar Chatterjee, Manas Bhikchand Mutha, Ho-Chi Chen, Prosenjit Sinha, Yongtao Liu
  • Patent number: 11941065
    Abstract: Systems and methods are described for generating record clusters. The methods comprise receiving a plurality of records from data sources and providing at least a subset of the records to a scoring model that determines scores for various pairings of the records, a score for a given pair of the records representing a probability that the given pair of records contain data elements about the same entity. The method further comprises generating a graph data structure that includes a plurality of nodes, individual nodes representing a different record from the records. The method also comprises assigning a different unique identifier to individual clusters of the final clusters and responding to a request for data regarding a given entity by providing aggregated data elements from those records of the records associated with a cluster of the final clusters having an identifier that represents the given entity.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: March 26, 2024
    Assignee: Experian Information Solutions, Inc.
    Inventors: Hua Li, Sophie Liu, Yi He, Zhixuan Wang, Chi Zhang, Kevin Chen, Shanji Xiong, Christer Dichiara, Mason Carpenter, Mark Hirn, Julian Yarkony
  • Patent number: 11937932
    Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: March 26, 2024
    Assignees: TAICHUNG VETERANS GENERAL HOSPITAL, TUNGHAI UNIVERSITY
    Inventors: Chieh-Liang Wu, Chun-Te Huang, Cheng-Hsu Chen, Tsai-Jung Wang, Kai-Chih Pai, Chun-Ming Lai, Min-Shian Wang, Ruey-Kai Sheu, Lun-Chi Chen, Yan-Nan Lin, Chien-Lun Liao, Ta-Chun Hung, Chien-Chung Huang, Chia-Tien Hsu, Shang-Feng Tsai
  • Patent number: 11942420
    Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Cheng-Chi Chuang, Shang-Wen Chang, Yi-Hsun Chiu
  • Patent number: 11939603
    Abstract: A modified cutinase is disclosed. The cutinase has the modified amino acid sequence of SEQ ID NO: 2, wherein the modification is a substitution of asparagine at position 181 with alanine, or substitutions of asparagine at position 181 with alanine and phenylalanine at position 235 with leucine. The modified enzyme has improved PET-hydrolytic activity, and thus, the high-activity PET hydrolase is obtained, and the industrial application value of the PET hydrolase is enhanced.
    Type: Grant
    Filed: June 21, 2023
    Date of Patent: March 26, 2024
    Assignee: HUBEI UNIVERSITY
    Inventors: Chun-Chi Chen, Jian-Wen Huang, Jian Min, Xian Li, Beilei Shi, Panpan Shen, Yu Yang, Yumei Hu, Longhai Dai, Lilan Zhang, Yunyun Yang, Rey-Ting Guo
  • Patent number: 11940737
    Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu, Wei-Ti Hsu, Jui-Ping Chuang, Tzong-Sheng Chang, Kuei-Shun Chen, Meng-Wei Chen
  • Publication number: 20240098016
    Abstract: A method for performing adaptive multi-link aggregation dispatching control in multi-link operation architecture and associated apparatus are provided.
    Type: Application
    Filed: June 19, 2023
    Publication date: March 21, 2024
    Applicant: MEDIATEK INC.
    Inventors: Kuo-Wei Chen, Chia-Shun Wan, Cheng-En Hsieh, Po-Chi Chen
  • Publication number: 20240095137
    Abstract: Efficient and effective testing systems and methods are presented. In one embodiment, a system includes: a user interface configured to enable user interaction with the system; a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the DUTs are compute express link (CXL) protocol compliant; and a tester configured to direct testing of the plurality of DUTs, wherein the tester is configured to enable hot add of one of the plurality of DUTs without interfering with testing of the other DUTS. In one exemplary implementation, the DUTs are memory devices and the DUTs can operate as extended memory. The user interface can be utilized to indicate a pause to remove a DUT and to indicate a DUT has been added and to trigger a re-start. The added one of the plurality of DUTs can be automatically recognized by a host in a way that is transparent to users. The tester automatically directs the hot add in response to a user trigger.
    Type: Application
    Filed: March 31, 2023
    Publication date: March 21, 2024
    Inventors: Srdjan Malisic, Chi Yuan, Rebecca Qiu, Jenny Chen
  • Publication number: 20240097443
    Abstract: A source-network-load-storage coordination dispatching method in a background of a coupling of renewable energy sources, including: taking an expectation of a minimum grid operating cost in a dispatching cycle as an objective function; generating an approximate value function of an output of a set for generating electricity from renewable energy sources and a user load, and constructing a source-network-load-storage coordination dispatching model with combination of the objective function; obtaining forecast data of the output of a set for generating electricity from renewable energy sources and the user load, and inputting the forecast data into the dispatching model for solving; performing iterative updating on the approximate value function, importing the approximate value function after the iterative updating into the dispatching model for iterative solving, and terminating an iterative process until a solving result satisfies a preset convergence condition; and using a solving result of a last iteration
    Type: Application
    Filed: January 14, 2022
    Publication date: March 21, 2024
    Inventors: Feng Guo, Jian Yang, Lintong Wang, Jiahao Zhou, Yefeng Luo, Dongbo Zhang, Yuande Zheng, Guode Ying, Minzhi Chen, Xinjian Chen, Jie Yu, Weiming Lu, Chi Zhang, Yizhi Zhu, Binren Wang, Chenghuai Hong
  • Publication number: 20240096996
    Abstract: A semiconductor device includes a first dielectric layer, a stack of semiconductor layers disposed over the first dielectric layer, a gate structure wrapping around each of the semiconductor layers and extending lengthwise along a direction, and a dielectric fin structure and an isolation structure disposed on opposite sides of the stack of semiconductor layers and embedded in the gate structure. The dielectric fin structure has a first width along the direction smaller than a second width of the isolation structure along the direction. The isolation structure includes a second dielectric layer extending through the gate structure and the first dielectric layer, and a third dielectric layer extending through the first dielectric layer and disposed on a bottom surface of the gate structure and a sidewall of the first dielectric layer.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Lo-Heng Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20240095135
    Abstract: Efficient and effective testing systems and methods are presented. In one embodiment, a testing system includes: a user interface configured to enable user interaction with the system; a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the DUTs are compute express link (CXL) protocol compliant; and a tester configured to direct testing of the plurality of DUTs, wherein the tester manages testing of the plurality of DUTs, including managing CXL protocol aspects of the testing. In one exemplary implementation, the tester prevents testing of a first one of the plurality of DUTs from detrimentally interfering with testing of a second one of the plurality of DUTs.
    Type: Application
    Filed: March 31, 2023
    Publication date: March 21, 2024
    Inventors: Srdjan Malisic, Chi Yuan, Jenny Chen
  • Publication number: 20240097436
    Abstract: An electronic device and a method for protecting an equipment from voltage surge damage are provided. The method includes: electrically connecting an input terminal of a one-way pass circuit to a first equipment and electrically connecting an output terminal of the one-way pass circuit to a second equipment; electrically connecting an over-voltage check circuit to the output terminal and a regenerative resistor circuit, wherein the regenerative resistor circuit includes a resistor; detecting, by the over-voltage check circuit, a voltage of the output terminal; and electrically, by the over-voltage check circuit, connecting the output terminal to the resistor in response to the voltage being greater than a voltage threshold.
    Type: Application
    Filed: February 2, 2023
    Publication date: March 21, 2024
    Applicant: Bamboo Dynamics Corporation., Ltd.
    Inventors: Yuan Chen Chan, Chi-Ming Chuang
  • Patent number: 11935787
    Abstract: A semiconductor device includes a first gate structure disposed on a substrate and extending in a first direction. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode, first sidewall spacers disposed on opposing side faces of the first gate electrode and the first cap insulating layer and second sidewall spacers disposed over the first sidewall spacers. The semiconductor device further includes a first protective layer formed over the first cap insulating layer, the first sidewall spacers and the second sidewall spacers. The first protective layer has a ?-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui-Chi Chen, Hsiang-Ku Shen, Jeng-Ya Yeh
  • Patent number: 11936877
    Abstract: A video decoder can be configured to determine that a current block in a current picture of the video data is coded in an affine prediction mode; determine one or more control-point motion vectors (CPMVs) for the current block; identify an initial prediction block for the current block in a reference picture using the one or more CPMVs; determine a current template for the current block in the current picture; and determine an initial reference template for the initial prediction block in the reference picture; and perform a motion vector refinement process to determine a modified prediction block based on a comparison of the current template to the initial reference template.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: March 19, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Chun-Chi Chen, Han Huang, Zhi Zhang, Yao-Jen Chang, Yan Zhang, Vadim Seregin, Marta Karczewicz