Patents by Inventor Chi Chu

Chi Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240044850
    Abstract: The disclosure describes embodiments of an apparatus including a first gas chromatograph including a fluid inlet, a fluid outlet, and a first temperature control. A controller is coupled to the first temperature control and includes logic to apply a first temperature profile to the first temperature control to heat, cool, or both heat and cool the first gas chromatograph. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: October 16, 2023
    Publication date: February 8, 2024
    Inventors: Tsung-Kuan A. Chou, Shih-Chi Chu, Chia-Sheng Cheng, Li-Peng Wang, Chien-Lin Huang
  • Publication number: 20240046817
    Abstract: The present invention relates to an exchangeable optical principles demonstrating kit. The kit includes a retractable sleeve structure having a first end and a second end; a grating plate including a grating film; and a pinhole plate including a pinhole opening, wherein the grating plate is selectively attached to the retractable sleeve structure by a magnetic connection, to render the exchangeable optical principles demonstrating kit to form an optical interference principle demonstrating device, and the pinhole plate is selectively attached to the retractable sleeve structure by a magnetic connection, to render the exchangeable optical principles demonstrating kit to form an optical pinhole principle demonstrating device.
    Type: Application
    Filed: October 19, 2022
    Publication date: February 8, 2024
    Inventor: CHING-CHI CHU
  • Patent number: 11894336
    Abstract: An integrated fan-out (InFO) package includes a die, a plurality of conductive structures aside the die, an encapsulant laterally encapsulating the die and the conductive structure, and a redistribution structure. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns, a plurality of conductive vias, and a plurality of alignment marks. The routing patterns and the conductive vias are electrically connected to the die and the conductive structures. The alignment marks surround the routing patterns and the conductive vias. The alignment marks are electrically insulated from the die and the conductive structures. At least one of the alignment marks is in physical contact with the encapsulant, and vertical projections of the alignment marks onto the encapsulant have an offset from one another.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: February 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jhih-Yu Wang, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Yung-Chi Chu
  • Publication number: 20240038674
    Abstract: A package includes a die and a redistribution structure. The die has an active surface and is wrapped around by an encapsulant. The redistribution structure disposed on the active surface of the die and located above the encapsulant, wherein the redistribution structure comprises a conductive via connected with the die, a routing pattern located above and connected with the conductive via, and a seal ring structure, the seal ring structure includes a first seal ring element and a second seal ring element located above and connected with the first seal ring element, wherein the second seal ring element includes a seed layer sandwiched between the first seal ring element and the second seal ring element, and a top surface of the first seal ring element is substantially coplanar with a top surface of the conductive via.
    Type: Application
    Filed: October 5, 2023
    Publication date: February 1, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Chu, Hung-Jui Kuo, Jhih-Yu Wang, Yu-Hsiang Hu
  • Patent number: 11869418
    Abstract: A micro light emitting diode display panel including multiple pixel structures is provided. Each of the pixel structures includes at least one sub-pixel, which includes a first micro-light-emitting chip with a first light-emitting area and a second micro-light-emitting chip with a second light-emitting area smaller than the first light-emitting area. The first micro-light-emitting chip emits light corresponding to a first luminance interval according to a first operating current interval. The second micro light-emitting chip emits light corresponding to a second luminance interval according to a second operating current interval. A gray-scale value of the second luminance interval is lower than a gray-scale value of the first luminance interval. The first micro-light-emitting chip and the second micro light-emitting chip have the same light-emitting color. The second micro-light-emitting chip has a smaller slope of a tangent line to a luminance versus current curve than the first micro-light-emitting chip.
    Type: Grant
    Filed: October 30, 2022
    Date of Patent: January 9, 2024
    Assignee: PlayNitride Display Co., Ltd.
    Inventors: Shiang-Ning Yang, Yung-Chi Chu, Chang-Rong Lin, Yu-Ya Peng
  • Patent number: 11862614
    Abstract: A micro LED display device includes a substrate, micro LED units and a transparent insulation layer. The substrate includes conductive pads and conductive connecting portions. The conductive pads are disposed on the substrate. Each of the micro LED units includes a semiconductor epitaxial structure and electrodes. The electrodes are disposed on the semiconductor epitaxial structure, and each of the electrodes is connected to one of the conductive connecting portions adjacent to each other. The transparent insulation layer is disposed on the substrate and covers the conductive pads, the conductive connecting portions and the micro LED units, and the transparent insulation layer is filled between the electrodes of each of the micro LED units. The transparent insulation layer relative to a surface on each of the semiconductor epitaxial structures is of a first thickness and a second thickness, and the first thickness is different from the second thickness.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: January 2, 2024
    Assignee: PlayNitride Display Co., Ltd.
    Inventors: Yu-Hung Lai, Yung-Chi Chu, Pei-Hsin Chen, Yi-Ching Chen, Yi-Chun Shih
  • Patent number: 11862560
    Abstract: A package structure includes a semiconductor die and a first redistribution circuit structure. The first redistribution circuit structure is disposed on and electrically connected to the semiconductor die, and includes a first build-up layer. The first build-up layer includes a first metallization layer and a first dielectric layer laterally wrapping the first metallization layer, wherein at least a portion of the first metallization layer is protruded out of the first dielectric layer.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Chu, Hung-Jui Kuo, Yu-Hsiang Hu, Wei-Chih Chen
  • Patent number: 11854997
    Abstract: A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jhih-Yu Wang, Yung-Chi Chu, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20230392768
    Abstract: A highly efficient light extraction system for LED chip arrays, in which a multi-function domed lens overlays the LED chip array. A lower portion of the multi-function domed lens acts as a reflector, capturing wide-angle light emitted by the LED chips. An upper portion of the multi-function domed lens provides the function of a refractive lens. The multi-function domed lens provides improved light extraction efficiency over prior art embodiments, greater total light output, as well as a narrower light distribution pattern, with increased light intensity at the center of the beam.
    Type: Application
    Filed: August 15, 2022
    Publication date: December 7, 2023
    Applicant: DICON FIBEROPTICS, INC.
    Inventors: Jeffrey B. Lee, Tai-Chi Chu, Yen-Chih Liu, Ho-Shang Lee
  • Publication number: 20230378065
    Abstract: A package structure includes a semiconductor die and a first redistribution circuit structure. The first redistribution circuit structure is disposed on and electrically connected to the semiconductor die, and includes a first build-up layer. The first build-up layer includes a first metallization layer and a first dielectric layer laterally wrapping the first metallization layer, wherein at least a portion of the first metallization layer is protruded out of the first dielectric layer.
    Type: Application
    Filed: August 1, 2023
    Publication date: November 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Chu, Hung-Jui Kuo, Yu-Hsiang Hu, Wei-Chih Chen
  • Publication number: 20230369158
    Abstract: A semiconductor device includes an encapsulant including a first hollow region, a sensing die in the first hollow region of the encapsulant, and a redistribution structure disposed on the encapsulant and the sensing die and electrically coupled to the sensing die. A top width of the hollow region is greater than a bottom width of the hollow region. The redistribution structure includes a second hollow region which exposes a sensing area of the sensing die, and the redistribution structure is slanted downward from an edge of the device toward the sensing area.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Chu, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Tian Hu
  • Publication number: 20230360985
    Abstract: A package includes a die, an encapsulant, and a redistribution structure. The encapsulant laterally encapsulates the die. The redistribution structure is over the die and the encapsulant. The redistribution structure partially exposes the die. A top surface of the redistribution structure is slanted downward continuously from an edge of the package toward an interior of the package.
    Type: Application
    Filed: July 19, 2023
    Publication date: November 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Chu, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
  • Patent number: 11798893
    Abstract: A package includes a die and a redistribution structure. The die has an active surface and is wrapped around by an encapsulant. The redistribution structure disposed on the active surface of the die and located above the encapsulant, wherein the redistribution structure comprises a conductive via connected with the die, a routing pattern located above and connected with the conductive via, and a seal ring structure, the seal ring structure includes a first seal ring element and a second seal ring element located above and connected with the first seal ring element, wherein the second seal ring element includes a seed layer sandwiched between the first seal ring element and the second seal ring element, and a top surface of the first seal ring element is substantially coplanar with a top surface of the conductive via.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: October 24, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Chu, Hung-Jui Kuo, Jhih-Yu Wang, Yu-Hsiang Hu
  • Patent number: 11796515
    Abstract: The disclosure describes embodiments of an apparatus including a first gas chromatograph including a fluid inlet, a fluid outlet, and a first temperature control. A controller is coupled to the first temperature control and includes logic to apply a first temperature profile to the first temperature control to heat, cool, or both heat and cool the first gas chromatograph. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: October 24, 2023
    Assignee: Tricorntech Corporation
    Inventors: Tsung-Kuan A. Chou, Shih-Chi Chu, Chia-Sheng Cheng, Li-Peng Wang, Chien-Lin Huang
  • Patent number: 11798857
    Abstract: A composition for a sacrificial film includes a polymer, a solvent, and a plasticize compound having an aromatic ring structure. A package includes a die, through insulating vias (TIV), an encapsulant, and a redistribution structure. The die includes a sensing component. The TIVs surround the die. The encapsulant laterally encapsulates the die and the TIVs. The redistribution structure is over the die, the TIVs, and the encapsulant. The redistribution structure has an opening exposing the sensing component of the die. A top surface of the redistribution structure is slanted.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: October 24, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Chu, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
  • Publication number: 20230304626
    Abstract: A stand adjustment device has a tripod-connecting member, a connecting seat, a proximal clamping plate, a boom-connecting tube, a locking shaft, and a manual operating member. The connecting seat is rotatably located around the tripod-connecting member. The proximal clamping plate is detachably attached to a side of the connecting seat. One end of the locking shaft is movably disposed in the boom-connecting tube. The boom is slidably mounted through the boom-connecting tube and the locking shaft. The locking shaft is slidably mounted through the boom-connecting tube, the proximal clamping plate, and the connecting seat such that the boom-connecting tube is rotatable relative to the connecting seat. The manual operating member and the locking shaft are configured to clamp the boom-connecting tube, the proximal clamping plate, and the connecting seat therebetween into a locked condition.
    Type: Application
    Filed: May 30, 2023
    Publication date: September 28, 2023
    Inventors: PEI-CHI CHU, Cheng-Lin HO, CHI-CHIA HUANG, Wei-Ting CHEN
  • Publication number: 20230296204
    Abstract: A stand adjustment device has a tripod-connecting member, a connecting seat, a distal clamping plate, a boom-connecting tube, a locking shaft, and a manual operating member. The connecting seat is rotatably located around the tripod-connecting member. The distal clamping plate is detachably attached to a side of the connecting seat. One end of the locking shaft is movably disposed in the boom-connecting tube. The boom is slidably mounted through the boom-connecting tube and the locking shaft. The locking shaft is slidably mounted through the boom-connecting tube, the distal clamping plate, and the connecting seat such that the boom-connecting tube is rotatable relative to the connecting seat. The manual operating member and the locking shaft are configured to clamp the boom-connecting tube, the distal clamping plate, and the connecting seat therebetween into a locked condition.
    Type: Application
    Filed: May 30, 2023
    Publication date: September 21, 2023
    Inventors: PEI-CHI CHU, Cheng-Lin HO, CHI-CHIA HUANG, Wei-Ting CHEN
  • Patent number: 11764124
    Abstract: A semiconductor package includes a semiconductor die including a sensing component, an encapsulant laterally covering the semiconductor die, a through insulator via (TIV) and a dummy TIV penetrating through the encapsulant, a patterned dielectric layer disposed on the top surfaces of the encapsulant and the semiconductor die, a conductive pattern disposed on and inserted into the patterned dielectric layer to be in contact with the TIV and the semiconductor die, and a first dummy conductive pattern disposed on the patterned dielectric layer and connected to the dummy TIV. The top surface of the encapsulant is above and rougher than a top surface of the semiconductor die, and the sensing component is accessibly exposed by the patterned dielectric layer.
    Type: Grant
    Filed: March 27, 2022
    Date of Patent: September 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Chu, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Tian Hu
  • Publication number: 20230290733
    Abstract: A package structure includes a plurality of semiconductor die, an insulating encapsulant and a redistribution layer. Each of the plurality of semiconductor dies includes a semiconductor substrate, conductive pads disposed on the semiconductor substrate, conductive posts disposed on the conductive pads, and at least one alignment mark located on the semiconductor substrate. The insulating encapsulant is encapsulating the plurality of semiconductor dies. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the plurality of semiconductor dies.
    Type: Application
    Filed: May 17, 2023
    Publication date: September 14, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jhih-Yu Wang, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Yung-Chi Chu
  • Patent number: 11747248
    Abstract: A method for assessing the release performance of microcapsules comprising at least one volatile ingredient, the method comprising the steps of: a. applying a plurality of said microcapsules to an underlying surface; b. applying a kinetic frictional shear stress ? through a contact surface of a probe under a predefined load, a predefined contact surface area and a predefined shear rate to said plurality of microcapsules; and c. measuring the amount of the at least one volatile ingredient released per second from said microcapsules under said kinetic frictional shear stress ?.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: September 5, 2023
    Assignee: Givaudan SA
    Inventors: Shih-Chi Chu, Angus Peter Macmaster, Marcus James Goodall