Patents by Inventor Chien Lin

Chien Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105671
    Abstract: An apparatus for transferring an electronic component including a first platform, a second platform, an actuator mechanism, and a flexible push generator is provided. The first platform is configured to carry a carrier substrate. The second platform is configured to carry a target substrate. The actuator mechanism is configured to actuate the first platform and the second platform to approach and move away from each other. The flexible push generator is disposed near the first platform or the second platform and generating a plurality of flexible pushes toward the first platform and the second platform in response to the first platform and the second platform actuated in a way that the first platform and the second platform approach each other.
    Type: Application
    Filed: August 10, 2023
    Publication date: March 28, 2024
    Applicant: Stroke Precision Advanced Engineering Co., Ltd.
    Inventors: Chien-Shou Liao, Chingju Lin
  • Publication number: 20240102934
    Abstract: A test strip detecting system includes a test strip, a test strip detecting carrier and a mobile communication apparatus. The test strip detecting carrier includes a container structure, positioning markers and colorimetric calibrating blocks, and the colorimetric calibrating blocks are embedded inside the positioning markers. The test strip is placed in the container structure and reacts with a specimen to generate color blocks. The mobile communication apparatus controls an image capture unit to capture an original image of the test strip placed in the test strip detecting carrier; detects the positioning markers in the original image to obtain a plurality of coordinates of the positioning markers; performs image coordinate calibration according to the plurality of coordinates to generate a calibrated image; and performs a colorimetric calibration for the color blocks and the colorimetric calibrating blocks according to the calibrated image so as to generate a test result.
    Type: Application
    Filed: November 14, 2022
    Publication date: March 28, 2024
    Applicant: National Cheng Kung University
    Inventors: Yu-Cheng Lin, Wei-Chien Weng, Yi-Hsuan Chen
  • Publication number: 20240105128
    Abstract: A method for driving an electronic device includes the following steps: receiving a first image data, detecting a first frame rate corresponding to the first image data, generating at least one first scanning signal according to the first image data, receiving a second image data, detecting a second frame rate corresponding to the second image data, and generating at least one second scanning signal according to the second image data. The at least one first scanning signal has a first high voltage level value. The at least one second scanning signal has a second high voltage level value. When the first frame rate is different from the second frame rate, the first high voltage level value is different from the second high voltage level value.
    Type: Application
    Filed: August 16, 2023
    Publication date: March 28, 2024
    Inventors: Yu-Lin HSIEH, Chien-Hao KUO, Cheng-Shen PAN
  • Publication number: 20240105481
    Abstract: The present invention provides a latching guide structure arranged inside a door of semiconductor carrier. The latching guide structure comprises an upper latching part, a lower latching part, at least one elastic unit and a driver. Moreover, a first guiding portion of the upper latching part is matched with a second guiding portion of the lower latching part, therefore to define the installation space for the at least one elastic unit. On the other hand, the driver simultaneously actuates an upper actuating unit of the first guiding portion and a lower actuating unit of the second guiding portion to linearly move in reverse direction therebetween. The range of the linear motion of the upper actuating unit and the lower actuating unit represents the compression or extension of the at least one elastic unit, determining to control the open/close status of the upper latching part and the lower latching part.
    Type: Application
    Filed: November 28, 2022
    Publication date: March 28, 2024
    Inventors: MING-CHIEN CHIU, CHIH-MING LIN, CHENG-HAN CHOU, PO-TING LEE
  • Patent number: 11942543
    Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chou Lin, Yi-Cheng Chiu, Karthick Murukesan, Yi-Min Chen, Shiuan-Jeng Lin, Wen-Chih Chiang, Chen-Chien Chang, Chih-Yuan Chan, Kuo-Ming Wu, Chun-Lin Tsai
  • Publication number: 20240096895
    Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Jui-Chien Huang, Shih-Cheng Chen, Chih-Hao Wang, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Lo-Heng Chang, Shi Ning Ju, Guan-Lin Chen
  • Publication number: 20240094527
    Abstract: A defog lens for vehicles includes a lens barrel, a lens, and a hydrophilic layer. The lens barrel has an opening toward an object side. The lens is disposed in the lens barrel and is located at the opening. The hydrophilic layer covers a surface of the lens and includes silicone compounds. Water droplets condensed on the lens could form a sheet film sticking to the surface of the lens and hard to form spherical water droplets, thereby improving the problem that the field of view of the conventional lens is blocked by spherical water droplets, effectively improving the clarity of the image captured by the defog lens, and therefore the defog lens could be applied to various environments.
    Type: Application
    Filed: February 1, 2023
    Publication date: March 21, 2024
    Applicant: Calin Technology Co., Ltd.
    Inventors: CHIH-YUNG HSIAO, MENG-CHIEN TSAI, CYUAN-CONG LI, HONG-YEN LIN
  • Publication number: 20240096998
    Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin LIANG, Chij-chien CHI, Yi-Ying LIU, Chia-Hung CHU, Hsu-Kai CHANG, Cheng-Wei CHANG, Chein-Shun LIAO, Keng-chu LIN, KAi-Ting HUANG
  • Publication number: 20240097720
    Abstract: A self-loopback radio transmitter having a transmitter with a modulator configured to up-convert a first baseband signal into a first RF (radio frequency) signal in accordance with a first LO (local oscillator) signal, and a power amplifier configured to receive the first RF signal and output a second RF signal to be emitted by an antenna and a third RF signal to be looped back, wherein the third RF signal is magnetically coupled from the second RF signal; and a loopback network having a shielded serial inductor configured to receive the third RF signal and output a fourth RF signal, and a demodulator configured to down-convert the fourth RF signal into a second baseband signal in accordance with a second LO signal, wherein the shielded serial inductor has a serial inductor of spiral topology and a coil laid out on a lower metal layer.
    Type: Application
    Filed: October 13, 2022
    Publication date: March 21, 2024
    Inventors: Chia-Liang (Leon) Lin, Ting-Hsu Chien
  • Patent number: 11937174
    Abstract: An access point provides a hidden wireless network that is configured with a set of SSIDs so that the hidden network is discoverable with multiple different SSIDs. Based on detection of a probe request frame which indicates an SSID from a device, the access point determines if the SSID for which network availability is requested matches one of the SSIDs in the set. If the SSID does match one of those included in the set, the SSID correctly identifies the hidden network, and the access point responds with a probe response frame. Devices connected to the hidden network may have initiated the establishment of the connection with a different SSIDs despite the hidden network being a single wireless network. Scaling the number of supported SSIDs therefore does not impact the frequency with which the access point transmits beacon frames for the hidden network.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: March 19, 2024
    Assignee: Palo Alto Networks, Inc.
    Inventor: Ta Chien Lin
  • Patent number: 11931187
    Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: March 19, 2024
    Assignees: Chang Gung Medical Foundation Chang Gung Memorial Hospital at Keelung, Chang Gung Memorial Hospital, Linkou, Chang Gung University
    Inventors: Jiun-Jie Wang, Yi-Hsin Weng, Shu-Hang Ng, Jur-Shan Cheng, Yi-Ming Wu, Yao-Liang Chen, Wey-Yil Lin, Chin-Song Lu, Wen-Chuin Hsu, Chia-Ling Chen, Yi-Chun Chen, Sung-Han Lin, Chih-Chien Tsai
  • Publication number: 20240084135
    Abstract: A resin composition and uses thereof are provided. The resin composition includes: (A) an epoxy resin; (B) a bismaleimide resin; and (C) a first flame retardant having a structure of formula (I): Wherein Ar is a C3 to C18 heteroaryl or a C6 to C18 aryl; R1 is H or a C1 to C18 alkyl; and R2 and R3 are independently H, a C1 to C18 alkyl, a C3 to C18 heteroaryl, or a C6 to C18 aryl.
    Type: Application
    Filed: December 7, 2022
    Publication date: March 14, 2024
    Inventors: Tsung-Hsien LIN, Shur-Fen LIU, Pin CHIEN, Kai-Cheng YANG
  • Publication number: 20240090336
    Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chang-Lin YANG, Chung-Te LIN, Sheng-Yuan CHANG, Han-Ting LIN, Chien-Hua HUANG
  • Publication number: 20240088042
    Abstract: A semiconductor structure includes a dielectric layer over a substrate, a via conductor over the substrate and in the dielectric layer, and a first graphene layer disposed over the via conductor. In some embodiments, a top surface of the via conductor and a top surface of the dielectric layer are level. In some embodiments, the first graphene layer overlaps the via conductor from a top view. In some embodiments, the semiconductor structure further includes a second graphene layer under the via conductor and a third graphene layer between the dielectric layer and the via conductor. In some embodiments, the second graphene layer is between the substrate and the via conductor.
    Type: Application
    Filed: January 11, 2023
    Publication date: March 14, 2024
    Inventors: SHU-WEI LI, HAN-TANG HUNG, YU-CHEN CHAN, CHIEN-HSIN HO, SHIN-YI YANG, MING-HAN LEE, SHAU-LIN SHUE
  • Patent number: 11927312
    Abstract: The disclosure provides an electronic device, including a circuit board, multiple semiconductor components, a first light reflecting structure, and a second light reflecting structure. The circuit board includes a substrate, and the substrate may have a first surface and at least one side surface. The multiple semiconductor components are disposed on the first surface. The first light reflecting structure is disposed on the first surface. The second light reflecting structure is disposed on the first surface and the at least one side surface.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: March 12, 2024
    Assignee: Innolux Corporation
    Inventors: Chin-Chia Huang, Chieh-Ying Chen, Jia-Huei Lin, Chin-Tai Hsu, Tzu-Chien Huang, Fu-Sheng Tsai
  • Publication number: 20240076797
    Abstract: A susceptor assembly for supporting a crucible during a crystal growth process includes a susceptor base, a tubular sidewall connected to the susceptor base, and a removable sacrifice ring interposed between the susceptor base and the sidewall. Each of the susceptor base and the sidewall is formed of a carbon-containing material. The susceptor base has an annular wall and a shoulder extending radially outward from an outer surface of the annular wall. The sidewall has a first end that receives the annular wall to connect the sidewall to the susceptor base. The sacrifice ring has a first surface that faces the outer surface of the annular wall, a second surface that faces an interior surface of the sidewall, and a ledge extending outward from the second surface that engages the first end of the sidewall.
    Type: Application
    Filed: September 7, 2022
    Publication date: March 7, 2024
    Inventors: Hong-Huei Huang, Benjamin Michael Meyer, Chun-Sheng Wu, Wei-Chen Chou, Chen-Yi Lin, Feng-Chien Tsai
  • Patent number: 11920036
    Abstract: A rubber resin material with high dielectric constant and a metal substrate with high dielectric constant are provided. The rubber resin material with high dielectric constant includes a rubber resin composition with high dielectric constant and inorganic fillers. The rubber resin composition with high dielectric constant includes: 40 wt % to 70 wt % of a liquid rubber, 10 wt % to 30 wt % of a polyphenylene ether resin, and 20 wt % to 40 wt % of a crosslinker. A molecular weight of the liquid rubber ranges from 800 g/mol to 6000 g/mol. A dielectric constant of the rubber resin material with high dielectric constant is higher than or equal to 2.0.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: March 5, 2024
    Assignee: NAN YA PLASTICS CORPORATION
    Inventors: Te-Chao Liao, Hung-Yi Chang, Chien-Kai Wei, Chia-Lin Liu
  • Publication number: 20240074136
    Abstract: A static random access memory (SRAM) periphery circuit includes a first n-type transistor and a second n-type transistor that are disposed in a first well region of first conductivity type, the first well region occupies a first distance in a row direction equal to a bitcell-pitch of an SRAM array. The SRAM periphery circuit includes a first p-type transistor and a second p-type transistor that are disposed in a second well region of second conductivity type. The second well region occupies a second distance in the row direction equal to the bitcell-pitch of the SRAM array. The second well region is disposed adjacent to the first well region in the row direction.
    Type: Application
    Filed: November 9, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yangsyu LIN, Chi-Lung LEE, Chien-Chi TIEN, Chiting CHENG
  • Publication number: 20240072115
    Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.
    Type: Application
    Filed: February 13, 2023
    Publication date: February 29, 2024
    Inventors: Wei-Xiang You, Wei-De Ho, Hsin Yang Hung, Meng-Yu Lin, Hsiang-Hung Huang, Chun-Fu Cheng, Kuan-Kan Hu, Szu-Hua Chen, Ting-Yun Wu, Wei-Cheng Tzeng, Wei-Cheng Lin, Cheng-Yin Wang, Jui-Chien Huang, Szuya Liao
  • Patent number: D1018907
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: March 19, 2024
    Assignee: CHENG UEI PRECISION INDUSTRY CO., LTD.
    Inventors: Yun-Chien Lee, Yi-Ching Hsu, Pei-Yi Lin, Yu-Hung Su, Sheng-Yuan Huang, Chun-Fu Lin