Abstract: A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.

Abstract: In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers and at least one of the spacer has width changes along vertical direction of device. At least one of the first semiconductor layers has a composition different from another of the first semiconductor layers.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. At least one of the first semiconductor layers has a composition which changes along a stacked direction of the first semiconductor layers and second semiconductor layers.

Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.

Abstract: An inspection apparatus includes: an inspection apparatus includes: a stage configured to receive a photomask; a radiation source configured to emit a first radiation beam for inspecting the photomask; and an aperture stop configured to receive a second radiation beam reflected from the photomask through an aperture of the aperture stop, wherein the aperture is tangent at a center of the aperture stop.

Abstract: An opening is formed through a dielectric material layer to physically expose a top surface of a conductive material portion in, or over, a substrate. A metallic nitride liner is formed on a sidewall of the opening and on the top surface of the conductive material portion. A metallic adhesion layer including an alloy of copper and at least one transition metal that is not copper is formed on an inner sidewall of the metallic nitride liner. A copper fill material portion may be formed on an inner sidewall of the metallic adhesion layer. The metallic adhesion layer is thermally stable, and remains free of holes during subsequent thermal processes, which may include reflow of the copper fill material portion. An additional copper fill material portion may be optionally deposited after a reflow process.

Abstract: A computer program product embodied on a non-transitory computer readable medium of a control system includes a firmware program file, a signature detection module that causes a processor to detect whether a pre-defined signature is present; a booting module that causes the processor to perform, after it is determined that the pre-defined signature is not present in the main block, operations of power management and pin initiation included in the booting sequence; and a flashing module that causes the processor to perform, in response to receipt of a flashing command, a flashing operation that includes overwriting the firmware program file with an update firmware program file.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. At least one of the first semiconductor layers has a composition which changes along a stacked direction of the first semiconductor layers and second semiconductor layers.

Abstract: A motor drive system includes a precharge circuit having an intelligent charging and discharging mechanism. In terms of charging, a delay circuit can be used to delay a timing for turning on the low-impedance path, a detection circuit can also detect a system status and a battery voltage, and perform a discharge process in a non-driving mode and when the battery voltage continues to decrease. In the discharge process, a variety of applications can be realized using driving mechanism of the motor drive system.

Abstract: The invention relates to a method and system for establishing a connection between a vehicle network service and an external application. The method comprises: in a vehicle (102), defining (S1) a trusted hotspot device (104) external to a vehicle gateway (106), the trusted hotspot device being connected to the vehicle gateway; in the trusted hotspot device, receiving (S2) a request from an application external to the vehicle requesting access to a service (108) on the vehicle network (110) via the vehicle gateway; in the vehicle gateway, determining (S3) if the requested vehicle network service is available on the vehicle network (110); and if the requested vehicle network service is available on the vehicle network, configuring (S4) the vehicle gateway to allow the requesting application to communicate with the requested vehicle network service.

Abstract: The present disclosure provides a structure and a method to reduce electro-migration. An interconnect structure according to the present disclosure includes a conductive feature embedded in a dielectric layer, a capping barrier layer disposed over the conductive feature and the dielectric layer, and an adhesion layer sandwiched between the capping barrier layer and the dielectric layer. The adhesion layer includes a degree of crystallinity between about 40% and about 70%.

Abstract: An information handling system may include a management controller and a chassis having mounted therein at least one add-in card. The management controller may be configured to: retrieve connection information from the add-in card, the connection information indicating a physical location of the add-in card within the chassis; compare the connection information with expected connection information associated with the information handling system; determine that the physical location of the add-in card within the chassis is in conflict with a restriction associated with the add-in card; and transmit an error message based on the determining.

Abstract: In one example, an electronic device may include a display screen defining a plurality of display regions. Further, the electronic device may include a camera to capture an image of an operator of the electronic device. Furthermore, the electronic device may include a controller operatively coupled to the camera and the display screen. The controller may detect an orientation of the operator's face with respect to the display screen using the captured image. Further, the controller may determine a first display region of the plurality of display regions corresponding to the detected orientation of the operators face. Furthermore, the controller may activate the first display region to position a cursor of a pointing device within the first display region.

Abstract: A magnetic component includes a core and at least one coil. The core includes at least one outer leg and an inner leg. The inner leg is separated from an upper inner surface of the core. The inner leg is at least partially divided into a plurality of separated portions along a length direction of the inner leg. The at least one coil is wound around the inner leg.

Abstract: A magnetic component includes a core, at least one coil, a first heat dissipating member and a second heat dissipating member. The core includes at least one outer leg and an inner leg. The at least one coil is wound around the inner leg. The first heat dissipating member is disposed on a first side and a top side of the core. The second heat dissipating member is disposed on a second side and the top side of the core. The first heat dissipating member and the second heat dissipating member have a first joint region, a second joint region and a third joint region on the top side. Projections of the first joint region and the second joint region do not overlap with the inner leg. A projection of at least one of the first heat dissipating member and the second heat dissipating member overlaps with the inner leg.

Abstract: An optical virtual-circuit-switching network system and optical switches thereof are provided. The optical virtual-circuit-switching network system includes multiple optical switches. Each optical switch includes an optical outbound handling module, an optical pass around module, and an optical inbound handling module. The optical outbound handling module transmits optical signals to both the horizontal optical network subsystem and the vertical optical network subsystem. The optical pass around module transmits optical signals from the horizontal optical network subsystem to the vertical optical network subsystem, or transmits optical signals from the vertical optical network subsystem to the horizontal optical network subsystem. The optical inbound handling module outputs the selected optical signals to dense wavelength-division multiplexing transceivers and, through these transceivers, converts the optical signals into electrical signals before forwarding the data to the top-of-rack switches.

Abstract: A wafer stage includes an area for receiving a wafer. The wafer stage further includes a first sensor outside of the area for receiving the wafer. The wafer stage further includes a second sensor outside of the area of receiving the wafer, wherein the second sensor is spaced from the first sensor. The wafer stage further includes a first particle capture area outside of the area for receiving the wafer, wherein the first particle capture area is spaced from both the first sensor and the second sensor, a dimension of the first particle capture area in a first direction parallel to a top surface of the wafer stage is at least 26 millimeters (mm), a dimension of the first particle capture area in a second direction parallel to the top surface of the wafer stage is at least 33 mm, and the second direction is perpendicular to the first direction.

Abstract: An electronic device, including a sensing substrate, a scintillator layer, and an adjustable reflective layer, is provided. The scintillator layer is disposed on the sensing substrate. The adjustable reflective layer is disposed on the sensing substrate and includes a first electrode, a second electrode, and an electrophoretic layer. The first electrode is disposed on the scintillator layer. The second electrode is disposed on the first electrode. The electrophoretic layer is disposed between the first electrode and the second electrode. The second electrode surrounds the scintillator layer.

Abstract: A reality image reconstruction system includes: a sensing device for sensing an outdoor environment and objects therein to generate environmental parameters of the outdoor environment and object parameters of said objects; a cloud server for receiving the environmental parameters of the outdoor environment, the object parameters of said objects, and movement parameters of the sensing device to establish prediction parameters and physical parameters of said objects in the outdoor environment; a simulation device for establishing a virtual environment synchronized with the outdoor environment according to the environmental parameters of the outdoor environment, the object parameters, the prediction parameters and the physical parameters of said objects; and an interactive device for interacting with said objects realistically in the virtual environment according to the environmental parameters of the outdoor environment, the object parameters, the prediction parameters and the physical parameters of said object

Abstract: A backplane connector includes a shielded design that has wafers with signal terminals supported as edge-coupled terminal pairs for differential signaling. A ground shield is mounted on each wafer and provides a U-channel that partially shields each terminal pair. An insert can be provided to help connect the ground shield to a U-shield to provide U-shaped shielding structure substantially the entire way from a tail to a contact.