Patents by Inventor Chien Lin

Chien Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240072115
    Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.
    Type: Application
    Filed: February 13, 2023
    Publication date: February 29, 2024
    Inventors: Wei-Xiang You, Wei-De Ho, Hsin Yang Hung, Meng-Yu Lin, Hsiang-Hung Huang, Chun-Fu Cheng, Kuan-Kan Hu, Szu-Hua Chen, Ting-Yun Wu, Wei-Cheng Tzeng, Wei-Cheng Lin, Cheng-Yin Wang, Jui-Chien Huang, Szuya Liao
  • Publication number: 20240055273
    Abstract: A wet etching solution according to the present disclosure is an etching solution for selectively removing a second metal layer made of at least one of a cobalt-based material or a copper-based material from a semiconductor substrate while suppressing etching of a first metal layer made of a tungsten-based material, the first metal layer and the second metal layer being co-present on the semiconductor substrate, an oxide layer being formed on a surface layer of at least the at least one of a cobalt-based material or a copper-based material. The wet etching solution includes a solution in which a ?-diketone containing a trifluoromethyl group and a carbonyl group bonded together is dissolved in an organic solvent.
    Type: Application
    Filed: January 4, 2022
    Publication date: February 15, 2024
    Inventors: Takahisa TANIGUCHI, Chih-Chien LIN, Tatsuo MIYAZAKI
  • Patent number: 11900586
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Publication number: 20240048033
    Abstract: An induction motor with on-rotor slip power recovery may have a rotor and a stator element. The rotor element has a rotor winding system with a number of winding units wound-distributed for inducing a rotor magnetic field. Each winding unit has an induction and an augmentation subwinding. The induction subwinding has two legs of each a number of induction conductor segments. The induction subwinding induces an emf that drives a rotor current in the rotor winding system to generate a basic induction component for the rotor magnetic field when the induction conductor segments move in the stator element. The augmentation subwinding has two legs of each a number of augmentation conductor segments aligned parallel to the induction conductor segments. The augmentation subwinding being wound that the two legs of augmentation conductor segments are immediately next to each other and positioned mid-way between the two legs of induction conductor segments.
    Type: Application
    Filed: August 1, 2023
    Publication date: February 8, 2024
    Inventors: Pan-Chien LIN, Teng-Chang CHANG
  • Publication number: 20240044850
    Abstract: The disclosure describes embodiments of an apparatus including a first gas chromatograph including a fluid inlet, a fluid outlet, and a first temperature control. A controller is coupled to the first temperature control and includes logic to apply a first temperature profile to the first temperature control to heat, cool, or both heat and cool the first gas chromatograph. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: October 16, 2023
    Publication date: February 8, 2024
    Inventors: Tsung-Kuan A. Chou, Shih-Chi Chu, Chia-Sheng Cheng, Li-Peng Wang, Chien-Lin Huang
  • Publication number: 20240030854
    Abstract: A motor drive system includes a precharge circuit having an intelligent charging and discharging mechanism. In terms of charging, a delay circuit can be used to delay a timing for turning on the low-impedance path, a detection circuit can also detect a system status and a battery voltage, and perform a discharge process in a non-driving mode and when the battery voltage continues to decrease. In the discharge process, a variety of applications can be realized using driving mechanism of the motor drive system.
    Type: Application
    Filed: November 27, 2020
    Publication date: January 25, 2024
    Inventors: YU-LIANG CHEN, CHI-CHIEN LIN
  • Publication number: 20240016954
    Abstract: A composition for improving the solubility of poorly soluble substances is provided. The composition for improving the solubility of poorly soluble substances includes 60-97% by weight of cyclodextrin and/or a derivative thereof, 0.5-4% by weight of at least one water-soluble polymer and 0.4-30% by weight of at least one water-soluble stabilizer, wherein the at least one water-soluble stabilizer includes caffeine, and wherein the poorly soluble substance is a tyrosine kinase inhibitor.
    Type: Application
    Filed: September 21, 2023
    Publication date: January 18, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Wen-Chia HUANG, Yen-Jen WANG, Felice CHENG, Chia-Ching CHEN, Shao-Chan YIN, Chien Lin PAN, Tsan-Lin HU, Meng-Nan LIN, Kuo-Kuei HUANG, Maggie LU, Chih-Peng LIU
  • Publication number: 20240023227
    Abstract: A circuit board comprises a substrate with opposite first and second sides. A pair of plated through holes (PTHs) extends along z-axis. A pair of signal traces are made on the first side of the substrate and electrically coupled to the pair of the PTHs respectively to form a differential pair. A ground metal is made on the second side of the substrate, the ground metal has a clearance made therein. The ground metal extends fully overlapping with the full signal traces to eliminate reflection noise caused by a boundary between the clearance and the metal ground.
    Type: Application
    Filed: July 14, 2022
    Publication date: January 18, 2024
    Inventors: Ching-Shan CHANG, Kun-Tao TANG, Tsung-Ting TSAI, Chien-Lin CHEN
  • Patent number: 11877385
    Abstract: A circuit board comprises a substrate with opposite first and second sides. A pair of plated through holes (PTHs) extends along z-axis. A pair of signal traces are made on the first side of the substrate and electrically coupled to the pair of the PTHs respectively to form a differential pair. A ground metal is made on the second side of the substrate, the ground metal has a clearance made therein. The ground metal extends fully overlapping with the full signal traces to eliminate reflection noise caused by a boundary between the clearance and the metal ground.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: January 16, 2024
    Assignee: FIRST HI-TEC ENTERPRISE CO., LTD.
    Inventors: Ching-Shan Chang, Kun-Tao Tang, Tsung-Ting Tsai, Chien-Lin Chen
  • Publication number: 20240003827
    Abstract: In a mask review method, a vacuum is drawn in a vacuum chamber that contains an extreme ultraviolet (EUV) actinic mask review system including an EUV illuminator, a mask stage, a projection optics box, and an EUV imaging sensor. With the vacuum drawn, a position is adjusted of at least one component of the EUV actinic mask review system. After the adjusting and with the vacuum drawn, an actinic image is acquired of an EUV mask mounted on the mask stage using the EUV imaging sensor. The acquiring includes transmitting EUV light from the EUV illuminator onto the EUV mask and projecting at least a portion of the EUV light reflected by the EUV mask onto the EUV imaging sensor using the projection optics box.
    Type: Application
    Filed: January 4, 2023
    Publication date: January 4, 2024
    Inventors: Chien-Lin Chen, Danping Peng, Chih-Chiang Tu, Chih-Wei Wen, Hsin-Fu Tseng
  • Patent number: 11855092
    Abstract: In an embodiment, a method includes forming a plurality of semiconductor fins over a substrate, the plurality of semiconductor fins comprising a first fin, a second fin, a third fin, and a fourth fin; forming a first dielectric layer over the plurality of semiconductor fins, the first dielectric layer filling an entirety of a first trench between the first fin and the second fin; forming a second dielectric layer over the first dielectric layer, the second dielectric layer filling an entirety of a second trench between the second fin and the third fin, the forming the second dielectric layer comprising: forming an oxynitride layer; and forming an oxide layer; and forming a third dielectric layer over the second dielectric layer, the third dielectric layer filling an entirety of a third trench between the third fin and the fourth fin.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi Chen Ho, Yiting Chang, Lun-Kuang Tan, Chien Lin
  • Publication number: 20230400775
    Abstract: A method of controlling a wafer stage includes moving the wafer stage to position an immersion hood over a first sensor in the wafer stage. The method further includes moving the wafer stage to position the immersion hood over a second sensor in the wafer stage. The method further includes moving the wafer stage to position the immersion hood over a first particle capture area on the wafer stage after moving the wafer stage to position the immersion hood over the second sensor. The method further includes moving the wafer stage to define a routing track over the first particle capture area. The method further includes moving the wafer stage to position the immersion hood over an area for receiving a wafer on the wafer stage after defining the routing track over the first particle capture area.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 14, 2023
    Inventors: Yung-Yao LEE, Wei Chih LIN, Chih Chien LIN
  • Patent number: 11829781
    Abstract: A method of remotely modifying a basic input/output system (BIOS) configuration setting includes steps of: transmitting, by a remote computer, a modification instruction to a cloud server; transmitting, by the cloud server to a POS system, a new configuration value of the BIOS configuration setting contained in the modification instruction; determining, by an embedded controller of the POS system, whether the new configuration value is identical to an original configuration value of the BIOS configuration setting; and by the embedded controller when a result of the determination is negative, updating the BIOS configuration setting and transmitting a response instruction to the remote computer.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: November 28, 2023
    Assignee: FLYTECH TECHNOLOGY CO., LTD.
    Inventors: Li-Chun Chou, Shui-Chin Tsai, Ting-You Liou, Chien-Lin Su
  • Patent number: 11831506
    Abstract: A disclosed touchless provisioning method configures a baseboard management controller (BMC) of a bare metal server to include or support two or more network services for retrieving a configuration profile locator (CPL) identifying a network-accessible configuration file containing a server configuration profile (SCP). At least one of the network services may be invoked to retrieve the CPL and pass the CPL to a provisioning agent process configured to access the configuration file and configure the system in accordance with the SCP. The server may require a static IP address and the two or more network services may include at least one network service, such as a multicast domain name service (mDNS), suitable for use in conjunction with a static IP address system and at least one network service, such as a DHCP service, suitable for use in conjunction with servers that do not require a static IP address.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: November 28, 2023
    Assignee: Dell Products L.P.
    Inventors: Jon Vernon Franklin, Chien Lin Lee, Jun Gu, Alaric Joaquim Narcissius Silveira
  • Publication number: 20230377991
    Abstract: A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 23, 2023
    Inventors: Chien Lin, Kun-Yu Lee, Shahaji B. More, Cheng-Han Lee, Shih-Chieh Chang
  • Patent number: 11822499
    Abstract: An information handling system may include a management controller and information handling resources that are coupled to the management controller via a first communication channel and a second communication channel, each information handling resource having a first communication channel identifier, and each information handling resource having a second communication channel identifier. The management controller may query the information handling resources via the first communication channel to determine a first set of unique identifiers for the information handling resources; query the information handling resources via the second communication channel to determine a second set of unique identifiers for the information handling resources; and based on a comparison between the first set of unique identifiers and the second set of unique identifiers, create a mapping that correlates the first communication channel identifiers with the second communication channel identifiers.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: November 21, 2023
    Assignee: Dell Products L.P.
    Inventors: Chien-Lin Lee, Jon Vernon Franklin, Venkatesh Ramamoorthy, Jun Gu, Robert T. Stevens
  • Publication number: 20230369070
    Abstract: The present disclosure relates to a method for fabricating a system on integrated chip (SoIC) package. Particularly, a glue layer is deposited on sidewalls of semiconductor dies prior to depositing a dielectric filling material between the semiconductor dies. The glue layer may be a nitrogen containing layer, such as silicon nitride, silicon carbon nitride, and silicon oxygen nitride. The dielectric filling material may be a silicon oxide formed from TEOS or mDEOS. The glue layer increases adhesion between the dielectric filling material and semiconductor dies.
    Type: Application
    Filed: August 31, 2022
    Publication date: November 16, 2023
    Inventors: Yi Chen HO, Chien LIN
  • Publication number: 20230350826
    Abstract: An information handling system may include a management controller and information handling resources that are coupled to the management controller via a first communication channel and a second communication channel, each information handling resource having a first communication channel identifier, and each information handling resource having a second communication channel identifier. The management controller may query the information handling resources via the first communication channel to determine a first set of unique identifiers for the information handling resources; query the information handling resources via the second communication channel to determine a second set of unique identifiers for the information handling resources; and based on a comparison between the first set of unique identifiers and the second set of unique identifiers, create a mapping that correlates the first communication channel identifiers with the second communication channel identifiers.
    Type: Application
    Filed: April 27, 2022
    Publication date: November 2, 2023
    Applicant: Dell Products L.P.
    Inventors: Chien-Lin LEE, Jon Vernon FRANKLIN, Venkatesh RAMAMOORTHY, Jun GU, Robert T. STEVENS
  • Publication number: 20230350823
    Abstract: An information handling system may include a management controller and a chassis having mounted therein at least one add-in card. The management controller may be configured to: retrieve connection information from the add-in card, the connection information indicating a physical location of the add-in card within the chassis; compare the connection information with expected connection information associated with the information handling system; determine that the physical location of the add-in card within the chassis is in conflict with a restriction associated with the add-in card; and transmit an error message based on the determining.
    Type: Application
    Filed: April 27, 2022
    Publication date: November 2, 2023
    Applicant: Dell Products L.P.
    Inventors: Robert R. LEYENDECKER, Jun GU, Chien-Lin LEE, Jon Vernon FRANKLIN
  • Patent number: 11801310
    Abstract: A composition for improving the solubility of poorly soluble substances is provided. The composition includes about 40-99.5% by weight of cyclodextrin and/or derivatives thereof; about 0.05-10% by weight of at least one water-soluble polymer; and about 0.05-60% by weight of at least one water-soluble stabilizer.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: October 31, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Wen-Chia Huang, Yen-Jen Wang, Felice Cheng, Chia-Ching Chen, Shao-Chan Yin, Chien-Lin Pan, Tsan-Lin Hu, Meng-Nan Lin, Kuo-Kuei Huang, Maggie Lu, Chih-Peng Liu