Abstract: A card reading apparatus for multi-directional data transmission is provided, including a USB interface, a memory card interface, an ATA/ATAPI interface, and a USB OTG controller. The USB OTG controller is connected to the USB interface, the memory card interface, and the ATA/ATAPI interface so that the USB media device connected to the USB interface, the flash memory cards connected to the memory card interface, and the data storage devices, such as hard disk and CD-R/W, connected to the ATA/ATAPI interface can all perform multi-directional data transfer among themselves.

Abstract: A highly efficient data characteristic identification device for flash memory is provided, including an instruction register, a plurality of auxiliary controllers, a data register, an address register, a microprocessor, a plurality of hash function units, a hash table unit, a comparator, a shifter, and an adder. By connecting the instruction register, data register and address register to a flash memory access control circuit and flash memory for storing the control instruction of the access control circuit and the data and physical and logical address of the flash memory, the control instruction is decoded and transmitted by the microprocessor and the auxiliary controllers to each circuit. A plurality of hash function units, a hash table unit, a comparator, a shifter, and an adder form an index computation circuit for flash memory LBA. By using the index and computation on the contents of the hash function units, the data characteristics of the LBA can be stored with less memory and higher efficiency.

Abstract: The present invention provides an OTG device for multi-directionally transmitting GPS data and a controlling method of the same. The OTG device is capable of automatically being switched as a master or slave devices based on a type of an external device connected thereto, thereby preventing a conflict between the OTG device and other external devices. Therefore, the GPS data received by a GPS module of the OTG device can easily be transmitted to the external device. Furthermore, the OTG device and the associated controlling method can be utilized in a multimedia device, such that the multimedia device is capable of GPS positioning, and multi-directionally transmitting GPS data and image data to be stored.

Abstract: A system and a method for configuration and management of flash memory is provided, including a flash memory, a virtual memory region, and a memory logical block region. The flash memory includes a plurality of physical erase units. Each physical erase unit is configured to include at least a consecutive segment, and each segment is configured to include at least a consecutive frame. Each frame is configured to include at least a consecutive page. Each virtual memory region is configured to include a plurality of areas, and each area is configured to include at least a virtual erase unit. The memory logical block region is configured to include a plurality of clusters, and each cluster includes at least a consecutive memory logical block.

Abstract: A pharmaceutical composition useful for hepatoprotection is provided. The composition comprises an effective amount of kinsenoside or a pharmaceutically acceptable salt or ester thereof. An aqueous extract of Anoectochilus spp. is also provided. The extract is substantially free of ethyl acetate-philic components.

Abstract: The present invention discloses a multimedia adapting apparatus. The multimedia adapting apparatus includes a communicating module, a buffer, a primary controller, a command register, a status register, a secondary controller, a media hardware engine, and a memory unit. The buffer stores the audiovisual content from the multimedia player. The primary controller handles the operation of audiovisual content between the multimedia player and the portable multimedia devices. The status register stores a plurality of statuses associated with the portable multimedia devices. The command register stores a command set associated the operation of audiovisual content between the multimedia player and the portable multimedia devices according to the statuses of the status register. The communicating module couples the buffer and the primary controller, respectively, to the multimedia player, for communicating with the multimedia player based on a plurality of control signals associated with the command set.

Abstract: A wireless transmitted electrocardiogram monitoring device is disclosed. A conductive fabric of the device features on that it is used to be a sensing component with characters of comfort, air permeability, softness, and stretchability thus achieves long-term signal measurement. The processing and transmission method of electrocardiogram signals is characterized in the wireless transmission of the electrocardiogram signals being detected. The signal receiving component (part) is for collecting data, displaying, storage, output and calculation of values. Therefore, a wireless transmitted electrocardiogram monitoring device is applied for long-term monitoring of the physical status of users.

Abstract: A caching device is positioned between a memory read/write controller and a flash memory, which contains an instruction register, a logical address register, a data register, a pair of auxiliary controllers, a microprocessor, an address translation unit, a flash memory address register, a caching control unit, and a caching instruction and data buffer area. Among them, the microprocessor is the core of the caching device responsible not only for the reading and writing the flash memory but also for the caching operation for logical and physical address translation. The caching control unit is a programmable device containing the instruction and data for caching the logical and physical address mapping. The caching instruction and data buffer area temporarily stores the caching instruction and data used by the caching control unit.

Abstract: A method of facilitating reliably accessing flash memory is provided. During the write-in process, the present invention utilizes the steps of coding write-in data to generate extra data, and then generating the first error correction code by performing an error-correcting operation on the write-in data and the extra data. Finally, store the N write-in data and the generated K extra data into the data area and the first ECC into the spare area. During read process, the present invention utilizes the steps of reading data from the data area of the target flash-memory page to generate the second ECC, counting with the counter a number of bit differences between the first ECC and the second ECC, and selecting M data from the N write-in data and the K extra data as decoding factors to retrieve the N write-in data. The higher the counter values, the lower the likelihood the corresponding bit is selected to be retrieved.

Abstract: A method is disclosed for manufacturing soft shoes, wherein the vamp, the insole and the outsole of the soft shoe are combined integrally, so that the soft shoe has an integrally formed structure, thereby enhancing the aesthetic quality of the soft shoe, and thereby enhancing the lifetime of the soft shoe. In addition, the soft shoe has a protective paint layer coated around the peripheral surface of the insole and the outsole, so that the protective paint layer is distributed around the surface of the soft shoe evenly and smoothly.

Abstract: A caching method provides a cashing mechanism between a logical addresses and a flash memory physical addresses. The cashing mechanism involves a search tree which contains a number of internal and external translation nodes. Each external translation node points to a link list of translation units, and each translation unit records a range of logical addresses and the corresponding range of physical addresses, in addition to a version value. By traversing the search tree to reach a translation unit, the physical address of a target logical address can be determined in an efficient manner. The version value of the translation unit can be used to determine the space taken up for storing the mapping of the logical and physical addresses should be released for reuse.

Abstract: An apparatus for improving the data access reliability of flash memory is provided, including an instruction register, an address register, a flash memory control circuit, a data register, an encoder, an error correction code (ECC) generator, a signal converter, a comparator, an arbitrator, and a decoder. The instruction register and the address register are connected to a flash memory respectively for storing the access instructions and the addresses. The flash memory control circuit is connected to both instruction register and address register for controlling the access to the flash memory. The data register is connected to flash memory control circuit for loading data to be written to the flash memory. The encoder encodes the written data, and the ECC generator generates an ECC, which is written to the flash memory through the signal converter. The comparator and the arbitrator provide the comparison with ECC and informing decoder f suspicious bit values when data is read from the flash memory.

Abstract: An apparatus for loading firmware into IC is provided, including a USB connector, at least a USB controller, a conversion interface, a plurality of connection interfaces, a plurality of non-volatile memories, and a plurality of IC slots. The USB connector provides the connection to any electronic USB device. The USB controller is connected to the USB connector for loading the original firmware data for the IC from the USB device. The conversion interface is connected to the USB controller for data format conversion of original firmware data between USB interface and conversion interface. The connection interfaces are connected to the conversion interface and the non-volatile memories are connected to the respective connection interfaces for storing the converted firmware data. The IC slots are connected to respective non-volatile memories so that the firmware stored in the non-volatile memories can be loaded into the ICs plugged in the IC slots.

Abstract: A self-contained ventilator includes a housing having a support member for supporting a pollution source. A filter is further disposed in the housing for filtering contaminants emitted from the pollution source. A conduit is adapted to connect to the housing to provide non-housing communication between portions of the housing. A fan is situated in the conduit to generate an airflow that follows a path through the housing, through the conduit, and back to the housing. The airflow entrains the contaminants such that the contaminants are captured by the filter upon passage of the airflow through the filter.

Abstract: A method for estimating crank angles and rotation speeds of an engine, having a signal processing unit to generate a dynamic sampling signal based on the tooth number signal of the crank detected by a crank angle sensor, an estimation unit designed by a discrete kinematic model and containing an estimator and a feedback gain matrix to read the dynamic sampling signal, and a crank rotation stroke discriminator allowing the signal processing unit to calculate a more precise crank dynamic sampling signal, so as to preclude external noises to interfering control of the engine.

Abstract: A system and a method for configuration and management of flash memory is provided, including a flash memory, a virtual memory region, and a memory logical block region. The flash memory includes a plurality of physical erase units. Each physical erase unit is configured to include at least a consecutive segment, and each segment is configured to include at least a consecutive frame. Each frame is configured to include at least a consecutive page. Each virtual memory region is configured to include a plurality of areas, and each area is configured to include at least a virtual erase unit. The memory logical block region is configured to include a plurality of clusters, and each cluster includes at least a consecutive memory logical block.

Abstract: A highly efficient data characteristic identification method for flash memory is provided, including the steps of: (a) based on the LBA corresponding to the write request to the flash memory, finding K corresponding counters in the hash table through K hash functions; (b) determining whether to perform decay period computation on hash table; if so, proceeding to step (c); otherwise, proceeding to step (d); (c) performing decay period computation on the hash table; (d) performing state update computation on the hash table; and (e) checking the hash table state and determining whether the data in the logic block corresponding to the flash memory is frequently updated. The method contains the decay period computation, state update computation, and checking on the data in the corresponding counters in the hash table to determine whether the data is frequently updated. Therefore, the object of a highly efficient data access characteristic identification method for flash memory is provided.

Abstract: A method of protecting confidential data using a non-sequential hidden block mechanism is provided, including the following steps of: (a) configuring the size of the confidential file; (b) the electronic host reading the capacity of the physical memory; (c) configuring the capacity of usable physical memory space; (d) the electronic host writing confidential data; (e) generating a random access lookup table (LUT) of address space; (f) using a random function to generate random address within a certain range and storing into the random LUT sequentially; and (g) sequentially mapping the logic addresses of the confidential data to the random LUT, and writing the mapped physical addresses to the physical memory blocks. Through the above steps, the mass storage device, such as no-volatile memory and hard disk, can store the data non-sequentially to achieve the object of confidential data protection.

Abstract: A highly efficient data characteristic identification device for flash memory is provided, including an instruction register, a plurality of auxiliary controllers, a data register, an address register, a microprocessor, a plurality of hash function units, a hash table unit, a comparator, a shifter, and an adder. By connecting the instruction register, data register and address register to a flash memory access control circuit and flash memory for storing the control instruction of the access control circuit and the data and physical and logical address of the flash memory, the control instruction is decoded and transmitted by the microprocessor and the auxiliary controllers to each circuit. A plurality of hash function units, a hash table unit, a comparator, a shifter, and an adder form an index computation circuit for flash memory LBA. By using the index and computation on the contents of the hash function units, the data characteristics of the LBA can be stored with less memory and higher efficiency.

Abstract: An air supply control device includes a fixed sleeve mounted on and extended into an air-pressure regulator to communicate an external environment with an air passage in the regulator while the air passage is communicable with a mouthpiece, and a control plate and a push-button control unit mounted in the fixed sleeve with a front flat plate of the control plate extended across the air passage of the regulator. When the push-button control unit is axially pushed, the control plate is turned to different angular position to thereby change a sectional area of the air passage. A diver may therefore control the air volume supplied from the air-pressure regulator via the air passage to the diver depending on a diving depth simply by pushing the push-button control unit to different axial position.