Patents by Inventor Chi Lee

Chi Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240020998
    Abstract: A character recognition method includes the stages as detailed in the following paragraph. An image is received, wherein the image is one in a plurality of consecutive images. A target object in the image is detected. Object information of the target object is defined according to the area ratio of the target object occupied in the image. Whether the target object in the image is the same as the target object in the previous image is determined according to the object information. Character recognition on the target object is performed to obtain a recognition result. The weighting score of the recognition result is calculated according to the object information and the recognition result. The weighting score of the recognition result of the target object in the consecutive images is accumulated until the weighting score is higher than a preset value, and the recognition result is output.
    Type: Application
    Filed: October 12, 2022
    Publication date: January 18, 2024
    Inventors: Chen-Chung LEE, Chia-Hung LIN, Chun-Hung CHEN, Chien-Kuo HUNG, Wen-Kuang CHEN, En-Chi LEE
  • Publication number: 20240008184
    Abstract: An electronic device is disclosed. The electronic device includes a carrier including a first portion, a second portion over the first portion, and a third portion connecting the first portion and the second portion. The electronic device also includes a first electronic component disposed between the first portion and the second portion. An active surface of the first electronic component faces the second portion. The electronic device also includes a second electronic component disposed over the second portion. The first portion is configured to transmit a first power signal to a backside surface of the first electronic component opposite to the active surface.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chiung-Ying KUO, Hung-Chun KUO, Pao-Nan LEE, Jung Jui KANG, Chang Chi LEE
  • Patent number: 11863885
    Abstract: The present disclosure provides a time delay integration (TDI) sensor using a rolling shutter. The TDI sensor includes two pixel arrays each having multiple pixel columns. Each pixel column includes multiple pixels arranged in an along-track direction, wherein two adjacent pixels or two adjacent pixel groups in every pixel column have a separation space therebetween. The separation space is equal to a pixel height multiplied by a time ratio of a line time difference of the rolling shutter and a frame period, or equal to a summation of at least one pixel height and a multiplication of the pixel height by a time ratio of the line time difference and the frame period. The TDI sensor doubles a number of times of integrating pixel data corresponding to the same position of a scene by arranging two separately operated pixel arrays.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: January 2, 2024
    Assignee: PIXART IMAGING INC.
    Inventors: Ren-Chieh Liu, Chao-Chi Lee
  • Publication number: 20230420418
    Abstract: An electronic device is provided. The electronic device includes a first die and a second die. The second die is disposed over the first die. A backside surface of the second die faces a backside surface of the first die. An active surface of the second die is configured to receive a first power. The second die is configured to provide the first die with a second power through the backside surface of the second die and the backside surface of the first die.
    Type: Application
    Filed: June 22, 2022
    Publication date: December 28, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun-Yen TING, Pao-Nan LEE, Jung Jui KANG, Chang Chi LEE
  • Publication number: 20230420413
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface; a redistribution layer (RDL) having a surface, wherein the first surface of the first die is on and electrically coupled to the surface of the RDL by non-solder interconnects; and a second die at the second surface of the first die, wherein the second die is electrically coupled directly to the second surface of the first die by solder interconnects.
    Type: Application
    Filed: June 23, 2022
    Publication date: December 28, 2023
    Applicant: Intel Corporation
    Inventors: Alois Nitsch, Han-Wen Lin, Yin-Ying Chen, Meng-Chi Lee, Andreas Dost, Hans Gerard Jetten
  • Publication number: 20230420416
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a carrier, a first electronic component, a second electronic component, a third electronic component, a fourth electronic component, and a connection element. The first electronic component is disposed over a surface of the carrier. The second electronic component is disposed over the first electronic component. The third electronic component is spaced apart from the first electronic component and disposed over the surface of the carrier. The fourth electronic component is disposed over the third electronic component. The connection element is electrically connecting the second electronic component to the fourth electronic component.
    Type: Application
    Filed: September 12, 2023
    Publication date: December 28, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Chi LEE, Jyan-Ann HSIA
  • Patent number: 11849236
    Abstract: The present disclosure provides a time delay integration (TDI) sensor using a rolling shutter. The TDI sensor includes multiple pixel columns. Each pixel column includes multiple pixels arranged in an along-track direction, wherein two adjacent pixels or two adjacent pixel groups in every pixel column have a separation space therebetween. The separation space is equal to a pixel height multiplied by a time ratio of a line time difference of the rolling shutter and a frame period, or equal to a summation of at least one pixel height and a multiplication of the pixel height by the time ratio of the line time difference and the frame period. The TDI sensor further records defect pixels of a pixel array such that in integrating pixel data to integrators, the pixel data associated with the defect pixels is not integrated into corresponding integrators.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: December 19, 2023
    Assignees: PIXART IMAGING INC., TAIWAN SPACE AGENCY
    Inventors: Ren-Chieh Liu, Chao-Chi Lee, Yi-Yuan Chen, En-Feng Hsu
  • Publication number: 20230374743
    Abstract: In some aspects, the techniques described herein relate to a passenger motor vehicle including a robotic arm configured for use in performing an additive manufacturing operation. A method is also disclosed.
    Type: Application
    Filed: May 18, 2022
    Publication date: November 23, 2023
    Inventors: Brendan Diamond, David Brian Glickman, Keith Weston, Stuart C. Salter, John Robert Van Wiemeersch, Ellen Cheng-chi Lee
  • Patent number: 11794404
    Abstract: A method of additive manufacturing a part via vat photopolymerization (VPP) includes irradiating a first material through a first transparent wall of a first material tank and forming a first section of an nth layer of the part on a platform, positioning the platform with the first section of the nth layer in a second material tank with a distance between the first section of the nth layer and a second transparent wall, and irradiating a second material such that a second section of the nth layer of the part is formed on the platform adjacent to the first section of the nth layer. The method repeats forming first and second sections of additional layer until a predetermined number of total layers are formed. Positioning the first and second sections with a distance between the second and first transparent walls, respectively, inhibits crashing during forming of the part.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: October 24, 2023
    Assignee: Ford Global Technologies, LLC
    Inventors: Matthew Cassoli, Giuseppe Domenic Lacaria, Sushmit Chowdhury, Ellen Cheng-chi Lee
  • Publication number: 20230330222
    Abstract: A pharmaceutical composition for boosting an immune response contains TREM-like transcript-1 (TREML1) extracellular domain (ECD) or stalk polypeptide. The TREML1 ECD or stalk polypeptide is derived from human or mouse TREML1. The pharmaceutical composition further contains an antigen as a vaccine, wherein the TREML1 ECD or stalk polypeptide functions as an adjuvant or immune booster.
    Type: Application
    Filed: May 14, 2021
    Publication date: October 19, 2023
    Applicant: Ascendo Biotechnology, Inc.
    Inventors: Yen-Ta Lu, Chia-Ming Chang, Ping-Yen Huang, I-Fang Tsai, Frank Wen-Chi Lee
  • Patent number: 11772310
    Abstract: A frame with an outer silicon layer and a manufacturing method of forming the silicone layer on the outer part of frame are disclosed. The manufacturing method includes a forming step, a combining step and a removing step. First, a pair of mold with a forming space is formed with a silicone carrier including an effective combination region and an ineffective region. An emplacing space is next formed in the effective combination region and a frame is put into the emplacing space. Before putting in the frame, either the outer part of frame or the emplacing space is coated with a silicone coating, and then the effective combination region is combined on the outer part of frame by a secondary sulfurization. Finally, the effective combination region is removed from the ineffective region to form a silicone layer, made of the effective combination region, on the outer part of frame.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: October 3, 2023
    Assignee: DRAGONSTATE TECHNOLOGY CO., LTD.
    Inventors: Kuo-Chi Lee, Chin-Hsing Lee, Lei Cheng
  • Patent number: 11764090
    Abstract: A tray includes a body for placement of a component (e.g. electronic component) and a taker disposed on a bottom surface of the body. The taker is used to take a spacer and includes a first taking element and a second taking element. The first taking element includes a first connection portion and a first confinement portion, and the second taking element includes a second connection portion and a second confinement portion. An accommodation space is provided between the first and second connection portions and a passageway is provided between the first and second confinement portions. While the spacer is moved through the passageway and into the accommodation space, it is confined in the accommodation space by the first and second confinement portions such that the taker can take away the spacer to show another tray located under the spacer as the tray is removed.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: September 19, 2023
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Hsu-Chi Lee, Pi-Yu Peng, Chun-Te Lee
  • Patent number: 11760784
    Abstract: A pharmaceutical composition for treating an ophthalmic disease in a subject includes a peptide and a pharmaceutically acceptable excipient, wherein the peptide contains the sequence of SEQ ID NO: 1: S-X-X-A-X-Q/H-X-X-X-X-I/V-I-X-R, wherein each X is independently any amino acid.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: September 19, 2023
    Assignee: BRIM Biotechnology, Inc.
    Inventors: Frank Wen-Chi Lee, Kuanyin Karen Lin, Yeou-Ping Tsao, Tsung-Chuan Ho
  • Publication number: 20230290809
    Abstract: A method of forming a semiconductor device includes: forming a passivation layer over a conductive pad that is disposed over a substrate; and forming an inductive component over the passivation layer, including: forming a first insulation layer and a first magnetic layer successively over the passivation layer; forming a first polymer layer over the first magnetic layer; forming a first conductive feature over the first polymer layer; forming a second polymer layer over the first polymer layer and the first conductive feature; patterning the second polymer layer, where after the patterning, a first sidewall of the second polymer layer includes multiple segments, where an extension of a first segment of the multiple segments intersects the second polymer layer; and after patterning the second polymer layer, forming a second insulation layer and a second magnetic layer successively over the second polymer layer.
    Type: Application
    Filed: May 31, 2022
    Publication date: September 14, 2023
    Inventors: Mei-Chi Lee, Chi-Cheng Chen, Wei-Li Huang, Kai Tzeng, Chun Yi Wu, Ming-Da Cheng
  • Publication number: 20230287161
    Abstract: A method of forming an etched part includes forming a substrate including a thermoset resin and etching a surface of the substrate. The thermoset resin includes a vat photopolymerization (VPP) thermoset resin and at least one of an etchable phase and etchable particles disposed within the VPP thermoset resin. The etching removes the etchable phase from the VPP thermoset resin at the surface of the substrate such that a plurality of micro-mechanical bonding sites are formed on an etched surface of the substrate.
    Type: Application
    Filed: May 18, 2023
    Publication date: September 14, 2023
    Applicant: Ford Global Technologies, LLC
    Inventors: Xiaojiang Wang, Shannon Christine Bollin, Robert D. Bedard, Matthew Cassoli, Ellen Cheng-chi Lee
  • Patent number: 11756927
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a carrier, a first electronic component, a second electronic component, a third electronic component, a fourth electronic component, and a connection element. The first electronic component is disposed over a surface of the carrier. The second electronic component is disposed over the first electronic component. The third electronic component is spaced apart from the first electronic component and disposed over the surface of the carrier. The fourth electronic component is disposed over the third electronic component. The connection element is electrically connecting the second electronic component to the fourth electronic component.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: September 12, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Chi Lee, Jyan-Ann Hsia
  • Publication number: 20230268293
    Abstract: An electronic device is disclosed. The electronic device includes a first electronic component and a power regulating structure configured to provide a first power to the first electronic component. The power regulating structure includes a first component and a second component at least partially overlapped with the first component from a top view.
    Type: Application
    Filed: February 18, 2022
    Publication date: August 24, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Pao-Nan LEE, Chen-Chao WANG, Chang Chi LEE
  • Publication number: 20230253302
    Abstract: An electronic package is disclosed. The electronic package includes an electronic component and a plurality of power regulating components. The plurality of power regulating components includes a first power regulating component and a second power regulating component. A first power path is established from the first power regulating component to a backside surface of the electronic component. A second power path is established from the second power regulating component to the backside surface of the electronic component.
    Type: Application
    Filed: February 10, 2022
    Publication date: August 10, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Pao-Nan LEE, Chen-Chao WANG, Chang Chi LEE
  • Publication number: 20230215810
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes an electronic component, and an inductance component. The protection layer encapsulates the electronic component and has a top surface and a bottom surface. The top surface and the bottom surface collectively define a space to accommodate the electronic component. The inductance component outflanks the space from the top surface and the bottom surface of the protection layer.
    Type: Application
    Filed: December 30, 2021
    Publication date: July 6, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Pao-Nan LEE, Chen-Chao WANG, Chang Chi LEE
  • Publication number: 20230210149
    Abstract: A method for preparing a fermented food by using a Rhizopus microsporus strain is provided. The method includes the following steps: providing an isolated and purified Rhizopus microsporus strain, and its deposit number is DSM 34400; and inoculating the isolated and purified Rhizopus microsporus strain to a substrate for fermentation to form a fermented food. The substrate includes a legume, a processing residue of a legume, or a combination thereof.
    Type: Application
    Filed: December 7, 2022
    Publication date: July 6, 2023
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chun-Shen CHENG, Chih-Hsuan FAN, Shu-Hsien TSAI, Chuan-Chi CHIEN, Shih-Chi LEE, Hsiang Tsai CHENG, Yu Lung HUANG