Patents by Inventor Chi Lee

Chi Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11588808
    Abstract: An operating system with automatic login mechanism and an automatic login method are provided. The operating system includes a first electronic device, a second electronic device and a server device. The second electronic device includes a biometric sensor. When a login event of the first electronic is triggered, the first electronic device sends a login request to the second electronic device directly or via the server device, so that the second electronic device performs a biometric verification by the biometric sensor according to the login request. When the biometric verification is passed, the second electronic device sends a first login credential to the first electronic device directly or via the server device, so that the first electronic device performs an automatic login operation of the first electronic device according to the first login credential.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: February 21, 2023
    Assignee: GoTrustID Inc.
    Inventors: Darren Tien-Chi Lee, Minglian Chen, Jeng-Lung Li, Yi-Kai Wang
  • Publication number: 20230009722
    Abstract: A process operating system includes a process control platform, a process operating platform and an endpoint task robot. The process control platform is configured to receive operation information, extract a task from the operation information using a semantic analysis method, and publish the task. The process operating platform is configured to receive the task and store the task in a task queue. After receiving the task, the process operating platform defines a processing flow based on the task, and sorts the order of the task in the task queue. The endpoint task robot is configured to automatically obtain the task from the process operation platform, executes the task according to the processing flow. It then writes the execution result into the log queue and transmits the execution result to the process control platform.
    Type: Application
    Filed: September 2, 2021
    Publication date: January 12, 2023
    Inventors: Chen-Chung LEE, Chun-Hung CHEN, Chien-Kuo HUNG, Wen-Kuang CHEN, En-Chi LEE
  • Patent number: 11542384
    Abstract: An additive article stabilizing method includes prior to polymerization, adding a radiation-activated stabilizing composition to a liquid resin, forming the article from the liquid resin, layer by layer, using radiation such that the stabilizing composition does not stabilize the liquid resin but the formed article, and neutralizing free radicals generated during a degradation process initiated by exposure of the article to additional radiation post-cure.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: January 3, 2023
    Assignee: Ford Global Technologies, LLC
    Inventors: Emily Ann Ryan, Mark Edward Nichols, Ellen Cheng-Chi Lee, Christopher Michael Seubert, Deborah Frances Mielewski, Nicholas Ryan Gunther, Matthew Linden Bedell
  • Publication number: 20220415851
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a carrier, a first electronic component, a second electronic component, a third electronic component, a fourth electronic component, and a connection element. The first electronic component is disposed over a surface of the carrier. The second electronic component is disposed over the first electronic component. The third electronic component is spaced apart from the first electronic component and disposed over the surface of the carrier. The fourth electronic component is disposed over the third electronic component. The connection element is electrically connecting the second electronic component to the fourth electronic component.
    Type: Application
    Filed: June 24, 2021
    Publication date: December 29, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Chi LEE, Jyan-Ann HSIA
  • Patent number: 11539086
    Abstract: Methods and systems for detecting and compensating for expansion of rechargeable batteries over time. An expansion detector may be coupled to or positioned proximate a rechargeable battery to monitor for expansion thereof. After expansion exceeding a selected threshold is detected, the expansion detector may report the expansion to an associated processing unit. The processing unit may undertake to arrest further rechargeable battery expansion by modifying or changing one or more characteristics of charging and/or discharging circuitry coupled to the rechargeable battery. For example, the processing unit may charge the rechargeable battery at a lower rate or with reduced voltage after detecting expansion.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: December 27, 2022
    Assignee: APPLE INC.
    Inventors: Daniel W. Jarvis, David M. DeMuro, Hongli Dai, Julian Malinski, Julien Marcil, Meng Chi Lee, Richard Hung Minh Dinh, Rishabh Bhargava, Steven D. Sterz, Richard M. Mank, Soundararajan Manthiri, Vijayasekaran Boovaragavan
  • Patent number: 11530133
    Abstract: A method for recovering lithium is provided. The method includes the following steps. A lithium-containing solution is provided. A manganese oxide adsorbent is immersed in the lithium-containing solution, and a reducing agent is added to carry out an adsorption reaction, and the manganese oxide adsorbent is immersed in a solution containing an oxidizing agent to carry out a desorption reaction.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: December 20, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Li-Ching Chung, Guan-You Lin, Yi Ting Wang, Chun-Chi Lee, Tzu Yu Cheng, Shing-Der Chen, Kuan-Foo Chang, Hsin Shao
  • Publication number: 20220392871
    Abstract: A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first processing element, a first I/O element, a second processing element, and a second I/O element. The first processing element is on a substrate. The first I/O element is on the substrate and electrically connected to the first processing element. The second processing element is on the substrate. The second I/O element is on the substrate and electrically connected to the second processing element. The first I/O element is electrically connected to and physically separated from the second I/O element.
    Type: Application
    Filed: June 3, 2021
    Publication date: December 8, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang Chi LEE, Jung Jui KANG, Chiu-Wen LEE, Li Chieh CHEN
  • Publication number: 20220384416
    Abstract: An array of poly lines on an active device area of an integrated chip is extended to form a dummy device structure on an adjacent isolation region. The resulting dummy device structure is an array of poly lines having the same line width, line spacing, and pitch as the array of poly lines on the active device area. The poly lines of the dummy device structure are on grid with the poly lines on the active device area. Because the dummy device structure is formed of poly lines that are on grid with the poly lines on the active device area, the dummy device structure may be much closer to the active device area than would otherwise be possible. The resulting proximity of the dummy device structure to the active device area improves anti-dishing performance and reduces empty space on the integrated chip.
    Type: Application
    Filed: August 5, 2022
    Publication date: December 1, 2022
    Inventors: Yung Feng Chang, Bao-Ru Young, Yu-Jung Chang, Tzung-Chi Lee, Tung-Heng Hsieh, Chun-Chia Hsu
  • Patent number: 11502088
    Abstract: A layout pattern of static random access memory at least includes a substrate, a plurality of fin structures on the substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate, the plurality of transistors include, a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, a second pull-down transistor PD2, a first pass gate transistor PG1, a second pass gate transistor PG2, a first read transistor RPD and a second read transistor RPG, and an additional fin structure, the additional fin structure is located between the fin structure of the first pass gate transistor PG1 and the fin structure of the second read transistor RPG.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: November 15, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Chi Lee, Shu-Wei Yeh, Chang-Hung Chen
  • Publication number: 20220358971
    Abstract: Some embodiments include an integrated assembly having first and second source/drain regions laterally offset from one another. Metal silicide is adjacent to lateral surfaces of the source/drain regions. Metal is adjacent to the metal silicide. Container-shaped first and second capacitor electrodes are coupled to the source/drain regions through the metal silicide and the metal. Capacitor dielectric material lines interior surfaces of the container-shaped first and second capacitor electrodes, A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends into the lined first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: February 10, 2022
    Publication date: November 10, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Che-Chi Lee, Terrence B. McDaniel, Kehao Zhang, Albert P. Chan, Clement Jacob, Luca Fumagalli, Vinay Nair
  • Publication number: 20220344450
    Abstract: Some embodiments include an integrated assembly having a laterally-extending container-shaped first capacitor electrode, and having a laterally-extending container-shaped second capacitor electrode laterally offset from the first capacitor electrode. Capacitor dielectric material lines interior surfaces and exterior surfaces of the container-shaped first and second capacitor electrodes. A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends along the lined interior and exterior surfaces of the first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: April 21, 2021
    Publication date: October 27, 2022
    Applicant: Micron Technology, Inc.
    Inventor: Che-Chi Lee
  • Publication number: 20220337589
    Abstract: An authentication system with an automatic authentication mechanism and an automatic authentication method are provided. The authentication system includes a server device and a gateway device. The gateway device is coupled to the server device. The gateway device is configured to act as a fast identity online (FIDO) client to send a gateway device registration data to register the gateway device in the server device acting as a FIDO server, and then the gateway device defines itself as initialized and connected. The gateway device periodically sends data to server device for authentication to maintain a trusted connection between the server device and the gateway device.
    Type: Application
    Filed: February 21, 2022
    Publication date: October 20, 2022
    Applicant: GoTrustID Inc.
    Inventors: Darren Tien-Chi Lee, Jeng-Lung Li, Ramesh Kesanupalli
  • Publication number: 20220328334
    Abstract: A tray includes a body for placement of a component (e.g. electronic component) and a taker disposed on a bottom surface of the body. The taker is used to take a spacer and includes a first taking element and a second taking element. The first taking element includes a first connection portion and a first confinement portion, and the second taking element includes a second connection portion and a second confinement portion. An accommodation space is provided between the first and second connection portions and a passageway is provided between the first and second confinement portions. While the spacer is moved through the passageway and into the accommodation space, it is confined in the accommodation space by the first and second confinement portions such that the taker can take away the spacer to show another tray located under the spacer as the tray is removed.
    Type: Application
    Filed: March 9, 2022
    Publication date: October 13, 2022
    Inventors: Hsu-Chi Lee, Pi-Yu Peng, Chun-Te Lee
  • Publication number: 20220288187
    Abstract: A hepatitis B virus (HBV) vaccine includes an HBV core antigen (HBcAg) and/or HBV surface antigen (HBsAg) formulated in nanocomplexes. The nanocomplexes contain chitosan and ?-PGA. These nanocomplexes containing HBc/sAg, chitosan, and ?-PGA can induce more balanced T helper cells (Th1 and Th2) polarization than can a conventional vaccine with an alum adjuvant. HBc/s-NC of the invention can elicit high levels of antibodies against HBsAg, a rapid elimination of HBsAg, and a slow decrease of HBeAg, indicating a phenomenon of HBsAg seroconversion. Thus, HBc/s-NC can overcome immune tolerance caused by chronic HBV infection to re-establish host immunity leading a functional cure.
    Type: Application
    Filed: September 23, 2020
    Publication date: September 15, 2022
    Applicant: Ascendo Biotechnology, Inc.
    Inventors: Ping-Yen HUANG, Frank Wen-Chi LEE, Yu-Hung CHEN, Yan-Wei WU
  • Patent number: 11442116
    Abstract: A detection circuit, including a first connecting terminal, an SPI bus, and a security component, is provided. The first connecting terminal is configured to be detachably connected to the main board. The security component is coupled to the first connecting terminal and the SPI bus. The security component forms a first loop with the main board, and is configured to detect a loop state of the first loop. The security component locks the SPI bus when the first loop is being detected by the security component to be disconnected.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: September 13, 2022
    Assignee: Wiwynn Corporation
    Inventors: Yu Shu Kao, Hsuan-Chih Kao, Yueh-Chi Lee, Yun-Chih Tsai
  • Patent number: 11426508
    Abstract: A snivel suction apparatus includes a suction mechanism and an air extraction mechanism. The air extraction mechanism is connected to the suction mechanism. The air extraction mechanism includes a pump, a piston, a communicating tube, a first check valve and a second check valve. The piston is arranged on the pump. One side of the communicating tube is connected to the pump. The other side of the communicating tube is connected to the suction mechanism. The first check valve is arranged in the pump and at one side of the communicating tube. The second check valve is arranged on the pump.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: August 30, 2022
    Assignee: TAI-SHINY TECHNOLOGY CO., LTD.
    Inventor: Chang-Chi Lee
  • Patent number: 11389995
    Abstract: An injection molding method for a semifinished product includes a semifinished product emplacement step, a semifinished product pre-compression step and a forming step. First, a pair of mold with a forming space is provided. A semifinished product is put into the mold, and a first joint is performed to the mold by a press-fit jig, fixing the semifinished product in the forming space. The semifinished product is also tightly fitted with the mold. Next, a first open-die is performed and the press-fit jig is removed. After that, a second joint is performed, and a forming material is injected into the forming space. Finally, a second open-die is performed, and then a finished product is formed. By the semifinished product pre-compression step, the forming material can be prevented from resulting in spill or burr on the semifinished product, thereby improving the yield of injection molding.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: July 19, 2022
    Assignee: DRAGONSTATE TECHNOLOGY CO., LTD.
    Inventors: Kuo-Chi Lee, Chin-Hsing Lee, Lei Cheng
  • Publication number: 20220224848
    Abstract: The present disclosure provides a time delay integration (TDI) sensor using a rolling shutter. The TDI sensor includes two pixel arrays each having multiple pixel columns. Each pixel column includes multiple pixels arranged in an along-track direction, wherein two adjacent pixels or two adjacent pixel groups in every pixel column have a separation space therebetween. The separation space is equal to a pixel height multiplied by a time ratio of a line time difference of the rolling shutter and a frame period, or equal to a summation of at least one pixel height and a multiplication of the pixel height by a time ratio of the line time difference and the frame period. The TDI sensor doubles a number of times of integrating pixel data corresponding to the same position of a scene by arranging two separately operated pixel arrays.
    Type: Application
    Filed: April 1, 2022
    Publication date: July 14, 2022
    Inventors: REN-CHIEH LIU, CHAO-CHI LEE
  • Publication number: 20220216220
    Abstract: A layout pattern of static random access memory at least includes a substrate, a plurality of fin structures on the substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate, the plurality of transistors include, a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, a second pull-down transistor PD2, a first pass gate transistor PG1, a second pass gate transistor PG2, a first read transistor RPD and a second read transistor RPG, and an additional fin structure, the additional fin structure is located between the fin structure of the first pass gate transistor PG1 and the fin structure of the second read transistor RPG.
    Type: Application
    Filed: February 1, 2021
    Publication date: July 7, 2022
    Inventors: Wei-Chi Lee, Shu-Wei Yeh, Chang-Hung Chen
  • Patent number: 11372466
    Abstract: A power saving method for a peripheral device in a wireless operation mode is provided. The power saving method at least includes the steps of allowing the peripheral device to enter an idle mode and judging whether the peripheral device receives a startup trigger event. In the idle mode, the light source in an operation region of the peripheral device is in an on state or a high-brightness state. If the peripheral device receives the startup trigger event, the peripheral device is switched from the idle mode to a power saving mode. In the power saving mode, the light source in the operation region of the peripheral device is in an off state or a low-brightness state. The peripheral device in the power saving mode consumes less electric power than the peripheral device in the idle mode.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: June 28, 2022
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Yun-Jung Lin, Shih-Chi Lee