Abstract: A method for forming a polysilicon film in a plasma-assisted chemical vapor deposition (CVD) system including a chamber in which a first electrode and a second electrode spaced apart from the first electrode are provided comprises providing a substrate on the second electrode, the substrate including a surface exposed to the first electrode, applying a first power to the first electrode for generating a plasma in the chamber, applying a second power to the second electrode during a nucleation stage of the polysilicon film for ion bombarding the surface of the substrate, and flowing an erosive gas into the chamber.

Abstract: A memory cell suitable for being disposed over a substrate is provided. The memory cell includes a poly-silicon island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-silicon island is disposed on the substrate and includes a source region, a drain region and a channel region located between the source and drain regions. The channel region has a plurality of regularly arranged tips thereon. The first dielectric layer is disposed on the poly-silicon island. The trapping layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the trapping layer. The control gate is disposed on the second dielectric layer. The memory cell mentioned above can be integrated into the LTPS-LCD panel or OLED panel.

Abstract: A heat sink layer is formed on portions of a substrate, and then an amorphous silicon layer is formed thereon. The heat coefficient of the sink layer is greater than that of the substrate. When an excimer laser heats the amorphous silicon layer to crystallize the amorphous silicon, nucleation sites are formed in the amorphous silicon layer on the heat sink layer. Next, laterally expanding crystallization occurs in the amorphous silicon layer on the substrate to form polysilicon having a crystal size of a micrometer.

Abstract: A method capable of making a semiconductor device in a plasma-assisted chemical vapor deposition (CVD) system including a chamber having a first electrode and a second electrode spaced apart from one another, the method comprising providing a substrate on the second electrode, the substrate including a surface being exposed to the first electrode, forming a semiconductor film on the surface of the substrate and applying a first bias to the second electrode during a nucleation stage of the semiconductor film till a predetermined thickness of the semiconductor film is reached, and applying a second bias to the second electrode after the predetermined thickness of the semiconductor film is reached.

Abstract: A device capable of converting solar radiation into electrical energy includes a substrate, and a plurality of cells formed over the substrate extending in parallel to each other, each of the plurality of cells including at least one thin film layer and having a size dependent on a film thickness distribution of a machine capable of forming the at least one thin film layer.

Abstract: A memory cell suitable for being disposed over a substrate is provided. The memory cell includes a poly-silicon island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-silicon island is disposed on the substrate and includes a source region, a drain region and a channel region located between the source and drain regions. The channel region has a plurality of regularly arranged tips thereon. The first dielectric layer is disposed on the poly-silicon island. The trapping layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the trapping layer. The control gate is disposed on the second dielectric layer. The memory cell mentioned above can be integrated into the LTPS-LCD panel or OLED panel.

Abstract: A memory cell suitable for being disposed over a substrate is provided. The memory cell includes a poly-silicon island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-silicon island is disposed on the substrate and includes a source region, a drain region and a channel region located between the source and drain regions. The channel region has a plurality of regularly arranged tips thereon. The first dielectric layer is disposed on the poly-silicon island. The trapping layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the trapping layer. The control gate is disposed on the second dielectric layer. The memory cell mentioned above can be integrated into the LTPS-LCD panel or OLED panel.

Abstract: A method of forming poly-silicon thin film transistors is described. An amorphous silicon thin film transistor is formed on a substrate, and then the Infrared (IR) heating process is used. A gate metal and source/drain metal are heated rapidly, and conduct heat energy to an amorphous silicon layer. Next, crystallization occurs in the amorphous silicon layer to form poly-silicon. Therefore a poly-silicon thin film transistor is produced.

Abstract: A memory cell suitable for being disposed over a substrate is provided. The memory cell includes a poly-silicon island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-silicon island is disposed on the substrate and includes a source region, a drain region and a channel region located between the source and drain regions. The channel region has a plurality of regularly arranged tips thereon. The first dielectric layer is disposed on the poly-silicon island. The trapping layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the trapping layer. The control gate is disposed on the second dielectric layer. The memory cell mentioned above can be integrated into the LTPS-LCD panel or OLED panel.

Abstract: A multi-layered complementary conductive line structure, a manufacturing method thereof and a manufacturing method of a TFT (thin film transistor) display array are provided. The process of TFT having multi-layered complementary conductive line structures does not need to increase the mask number in comparison with the currently process and is able to solve the resistance problem of the lines inside a display.

Abstract: A multi-layered complementary conductive line structure, a manufacturing method thereof and a manufacturing method of a TFT (thin film transistor) display array are provided. The process of TFT having multi-layered complementary conductive line structures does not need to increase the mask number in comparison with the currently process and is able to solve the resistance problem of the lines inside a display.

Abstract: A method for manufacturing a flexible panel is disclosed, which has the following steps. First, a first substrate having a plurality of functional switches or conducting lines thereon is provided. Then, a second substrate is bonded on the functional switches or conducting lines, and the first substrate is thinned to a predetermined thickness subsequently. Afterwards, a flexible third substrate is adhered on the first substrate, wherein the first substrate is sandwiched between the second substrate and the third substrate. Finally, the second substrate is removed.

Abstract: A method for fabricating a thin film transistor (“TFT”) device includes providing a substrate, forming a patterned amorphous silicon layer over the substrate including a pair of first regions, a second region disposed between the pair of first regions, and at least one third region, each of which being disposed between and contiguous with the second region and each of the pair of first regions, the second region including a sub-region contiguous with each of the at least one third region, forming a heat retaining layer over the substrate, irradiating the patterned amorphous silicon layer with a laser through the heat retaining layer to form a patterned crystallized silicon layer corresponding to the patterned amorphous silicon layer including a grain boundary extending substantially across a crystallized sub-region corresponding to the sub-region, and forming a patterned conductive layer over a portion of a crystallized second region of the patterned crystallized silicon layer corresponding to the second regi

Abstract: A structure of a thin film transistor and a method for making the same are provided. The structure includes a strip-shaped silicon island, a gate, and a first and second ion doping regions. The strip-shaped silicon island is a thin film region with a predetermined long side and short side, and farther has a plurality of lateral grain boundaries substantially parallel to the short side of the silicon island. The gate is located over the silicon island and substantially parallel to the lateral grain boundaries. The first and second ion doping regions, used as source/drain regions of the TFT, are located at two sides along the long side of the island and substantially perpendicular to the gate.

Abstract: A method for forming a polysilicon film in a plasma-assisted chemical vapor deposition (CVD) system including a chamber in which a first electrode and a second electrode spaced apart from the first electrode are provided comprises providing a substrate on the second electrode, the substrate including a surface exposed to the first electrode, applying a first power to the first electrode for generating a plasma in the chamber, applying a second power to the second electrode during a nucleation stage of the polysilicon film for ion bombarding the surface of the substrate, and flowing an erosive gas into the chamber.

Abstract: The present invention discloses an active organic light emitting diode (AOLED) display structure. A color filter and thin film transistor organic light emitting diode (TFT-OLED) are incorporated on one substrate of the AOLED. Moreover, a Indium Tin Oxide(ITO)layer of the AOLED is deposited with a black matrix layer so as to lower light leakage effect and increase the contrast and color purity level in between pixels of the display. By adopting such technology, a flat panel display having large area, high resolution and low product cost is accordingly implemented.

Abstract: A memory cell suitable for being disposed over a substrate is provided. The memory cell includes a poly-silicon island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-silicon island is disposed on the substrate and includes a source region, a drain region and a channel region located between the source and drain regions. The channel region has a plurality of regularly arranged tips thereon. The first dielectric layer is disposed on the poly-silicon island. The trapping layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the trapping layer. The control gate is disposed on the second dielectric layer. The memory cell mentioned above can be integrated into the LTPS-LCD panel or OLED panel.

Abstract: A method of manufacturing a TFT array panel for a LCD disclosers that the gate electrode wiring, transparent conducting electrode, and the first electrode of the storage capacity are formed while the first mask is processing. Then, the selective deposition method is used to process the growth of the first metal wiring. This, therefore, can reduce the numbers of the mask processes. Further, the metal deposition with photo-resist lift-off step is used to implement the layout of the second metal wiring for the consequent transmission lines in the manufacturing process. Finally, the process of the passivation layer deposition is used to implement associated circuits of a TFT array panel for a LCD. The TFT array panel for a LCD for manufacturing circuits can simplify the manufacturing process and reduce the cost.

Abstract: A memory cell, suitable for being disposed on a substrate, comprises a poly-Si island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-Si island is disposed on the substrate and includes a source doped region, a drain doped region and a channel region there-between. The first dielectric layer is disposed on the poly-Si island, the trapping layer is disposed on the first dielectric layer, the second dielectric layer is disposed on the trapping layer and the control gate is disposed on the second dielectric layer. The above-described memory cell can be integrated into the manufacturing process of a low temperature polysilicon LCD panel (LTPS LCD panel) or an organic light emitting display panel (OLED panel).

Abstract: A method for fabricating a semiconductor device includes providing a substrate, forming an amorphous silicon layer over the substrate, forming a heat retaining layer on the amorphous silicon layer, patterning the heat retaining layer, and irradiating the patterned heat retaining layer.