Abstract: A Graphics Processing Unit (GPU) concurrently executes kernel codes programmed in more than one programming framework. The GPU includes a first command decoder that decodes a first set of commands issued by a first Application Programming Interface (API) for executing a first kernel code. The GPU also includes a second command decoder that decodes a second set of commands issued by a second API for executing a second kernel code. The GPU also includes a plurality of shader cores and a pipe manager. According to decoded commands, the pipe manager assigns a first set of shader cores and a second set of shader cores to concurrently execute the first kernel code and the second kernel code, respectively.

Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A dielectric passivation layer is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer, and extend through the dielectric passivation layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. The gate electrode has an exterior surface. An oxygen containing region is embedded at least in the second III-V compound layer under the gate electrode. A gate dielectric layer has a first portion and a second portion. The first portion is under the gate electrode and on the oxygen containing region. The second portion is on a portion of the exterior surface of the gate electrode.

Abstract: A cable connector assembly includes a cable and a connector electrically connected with the cable for further electrically connecting with a power source. The connector includes: a main body; a plurality of contacts retained to the main body; a light emitting element; a printed circuit board (15) for controlling the light emitting element to emit light; and an outer case enclosing the connector and defining an indication area; wherein the connector further includes a conducting member mounted on the printed circuit board (15), the conducting member is a spring plate made of metal material pressing upon the indication area of the outer case, a front end of the outer case defines a transparent portion made of transparent material, and upon pressing the indication area, capacitance is affected and the light emitting element is turned on to emit light through the transparent portion.

Abstract: A wire-winding device comprising: an upper cover having a bottom surface and a slot deviating from a center of the bottom surface; a rotary base having an annular track on a top surface thereof, the annual track and the slot of the upper cover constituting an orbit; a spiral spring received in the rotary base; a transmission line winding around the rotary base; a lower cover assembled with the upper cover; and an elastic positioning element having a base and a positioning part extruding from the lower surface of the base, the base having an elastic part and a respective fixed part at each of two ends thereof, the elastic positioning element being moveable along the orbit in response to a rotational movement of the rotary base to avoid the transmission line to be tied a knot.

Abstract: A charging bracket for charging a consumer electronic product includes a first end, a second end, a connecting portion connecting the first end, a second end, a connecting portion, a first connector located at the first end and cooperating with the consumer electronic product, a second connector connecting with the first connector electrically, a coil located on the connecting portion, a wired charging loop comprising the first connector and the second connector and a wireless charging loop comprising the first connector and the coil, wherein the connecting portion is bendable to lie on a plane different from a plane defined by the first end and the second end.

Abstract: A transistor with a multi-layer active layer having at least one partial recess is provided. The transistor includes a channel layer arranged over a substrate. The channel layer has a first bandgap. The transistor includes a first active layer arranged over the channel layer. The first active layer has a second bandgap different from the first band gap such that the first active layer and the channel layer meet at a heterojunction. The transistor includes a second active layer arranged over the first active layer. The transistor also includes a dielectric layer arranged over the second active layer. The transistor further includes gate electrode having gate edges that are laterally adjacent to the dielectric layer. At least one gate edge of the gate edges is laterally separated from the second active layer by a first recess.

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

Abstract: A device includes insulation regions over portions of a semiconductor substrate, and a III-V compound semiconductor region over top surfaces of the insulation regions, wherein the III-V compound semiconductor region overlaps a region between opposite sidewalls of the insulation regions. The III-V compound semiconductor region includes a first and a second III-V compound semiconductor layer formed of a first III-V compound semiconductor material having a first band gap, and a third III-V compound semiconductor layer formed of a second III-V compound semiconductor material between the first and the second III-V compound semiconductor layers. The second III-V compound semiconductor material has a second band gap lower than the first band gap. A gate dielectric is formed on a sidewall and a top surface of the III-V compound semiconductor region. A gate electrode is formed over the gate dielectric.

Abstract: A method of forming a semiconductor structure includes depositing a first III-V layer over a substrate. The method includes depositing a first III-V compound layer over the first III-V layer. Depositing the first III-V compound layer includes depositing a lower III-V compound layer. Depositing the first III-V compound layer includes depositing an upper III-V compound layer over the lower III-V compound layer, wherein the first III-V layer has a doping concentration greater than that of the upper III-V compound layer. The method includes repeating depositing III-V compound layers until a number of III-V compound layers is equal to a predetermined number of III-V compound layers. The method includes forming a second III-V compound layer an upper most III-V compound layer, wherein the second III-V compound layer is undoped or doped. The method includes forming an active layer over the second III-V compound layer.

Abstract: The present disclosure provides a semiconductor structure, including a substrate, a first III-V layer over the substrate, having a first band gap, and a second III-V layer over the first III-V layer, having a second band gap. The second III-V layer includes a first surface in contact with the first III-V layer and a second surface opposite to the first surface. The second band gap at the second surface is greater than the second band gap at the first surface. The present disclosure also provides a manufacturing method of the aforesaid semiconductor structure.

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

Abstract: A wireless charger assembly is used for transferring power to an electronic device through inductive charging. The wireless charger assembly includes a bottom case releasably mounted to an exterior flatbed, a transmitter coil, and a top case. The transmitter coil transmits power to a receiver coil of the electronic device through inductive charging. The top case has a working platform mounted around the working surface of the flatbed, a neck portion extending downwardly from the working platform, and a slot defined by the working platform and the neck portion. The neck portion releasably retained to the closed loop wall.

Abstract: A semiconductor structure includes a substrate; and a graded III-V layer over the substrate. The semiconductor structure further includes a p-doped gallium nitride (GaN) layer over the graded III-V layer. The semiconductor structure further includes one or more sets of GaN layers over the p-doped GaN layer. Each set of the one or more sets of GaN layers includes a lower GaN layer, wherein the lower GaN layer is undoped, unintentionally doped having N-type doping, or N-type doped. Each set of the one or more sets of GaN layers includes an upper GaN layer on the lower GaN layer, wherein the upper GaN layer is P-type doped. The semiconductor structure includes a second GaN layer over the one or more sets of GaN layers, the second GaN layer being either undoped or unintentionally doped having the N-type doping. The semiconductor structure includes an active layer over the second GaN layer.

Abstract: A cable connector assembly (100) includes: a cable (30) having a number of inner wires; a first connector (10) including a main body (120), plural contacts (121) retained in the main body, a first circuit board (130), a luminous element (152), and a cover; and a second circuit board (180) assembled on a rear end of the first circuit board and getting power and grounding source from the first circuit board. The second circuit board includes a detection contact (182) electrically connected to an inner wire of the cable, and a chip (181) electrically connected respectively to the luminous element and the detection contact. The chip detects a voltage difference between the power source and the first connector. A light is emitted by the luminous element passing through the cover to indicate a charging status of the charging device.

Abstract: A laser pointer 100 includes a case (1), a laser module (2), a printed circuit board assembly (3) and a charging connector (6). The case (1) includes a lighting end (12) at a front end thereof, a mounting port (13) at a rear end thereof, a receiving cavity between the lighting end and the mounting port, and an inner wall (15). The laser module (2) and the printed circuit board assembly (3) are received in the receiving cavity (14). The printed circuit board assembly connects with the rear side of the laser module (2). The charging connector (6) mounted on the rear end of the printed circuit board assembly (3) electrically connects to the laser module (2) through the printed circuit board assembly (3).

Abstract: A wireless charger used for charging a portable electronic device with a receiver coil includes a wireless charging body, a transmitter coil, and a shaft. The charging body has a front body to support the portable electronic device and a rear body coordinated with the front body to form a receiving cavity for receiving transmitter coil. The rear body defines a track for the shaft disposing therein and moving the transmitter coil to align with the receiver coil. The wireless charger could align with receiver coils of different portable electronic devices.

Abstract: The present disclosure relates to a structure and method of forming a GaN film on a Si substrate that includes an additional or second high temperature (HT) AlN seed layer, introduced for reducing the tensile stress of GaN on a Si substrate. The second HT AlN seed layer is disposed over a first HT AlN seed layer, and has a low V/III ratio compared to the first HT AlN seed layer. The second HT AlN seed layer has better lattice matching between Si and GaN and this reduces the tensile stress on GaN. The additional HT AlN seed layer further acts as a capping layer and helps annihilate or terminate threading dislocations (TDs) originating from a LT AlN seed layer. The second HT AlN seed layer also helps prevent Si diffusion from the substrate to the GaN film.

Abstract: A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is smaller than the first band gap. The HEMT further includes a third III-V compound layer having a third band gap over the second III-V compound layer, wherein the third band gap is greater than the first band gap. A gate electrode is formed over the third III-V compound layer. A source region and a drain region are over the third III-V compound layer and on opposite sides of the gate electrode.

Abstract: A cable connector assembly includes a cable and a connector electrically connected with the cable for further electrically connecting with a power source. The connector includes: a main body; a plurality of contacts retained to the main body; a light emitting element; a first printed circuit board for controlling the light emitting element to emit light; and an outer case enclosing the connector and defining a conductive area; wherein the connector further includes a conducting member mounted on the first printed circuit board, the conducting member is a shrapnel made of metal material pressing upon the conductive area of the outer case, a front end of the outer case defines a transparent portion made of transparent material, and upon pressing the conductive area the light emitting element is turned on to emit light through the transparent portion.

Abstract: A method of manufacturing a semiconductor device includes forming a barrier structure over a substrate. The method further includes forming a channel layer over the barrier structure. The method further includes depositing an active layer over the channel layer. The method further includes forming source/drain electrodes over the channel layer. The method further includes annealing the source/drain electrodes to form ohmic contacts in the active layer under the source/drain electrodes.