Patents by Inventor Chi-Ming Chen

Chi-Ming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING A BARRIER STRUCTURE
    Publication number: 20160111520
    Abstract: A method of manufacturing a semiconductor device includes forming a barrier structure over a substrate. The method further includes forming a channel layer over the barrier structure. The method further includes depositing an active layer over the channel layer. The method further includes forming source/drain electrodes over the channel layer. The method further includes annealing the source/drain electrodes to form ohmic contacts in the active layer under the source/drain electrodes.
    Type: Application
    Filed: December 21, 2015
    Publication date: April 21, 2016
    Inventors: Po-Chun Liu, Chi-Ming Chen, Chen-Hao Chiang, Chung-Yi Yu, Chia-Shiung Tsai, Xiaomeng Chen
  • HIGH ELECTRON MOBILITY TRANSISTOR WITH INDIUM NITRIDE LAYER
    Publication number: 20160071969
    Abstract: A semiconductor device includes a substrate, a first layer over the substrate, a second layer over the first layer, and a third layer over the second layer. The third layer has a first portion and a second portion. The first portion of the third layer is separated from the second portion of the third layer. The semiconductor device also includes a first blended region beneath the first portion of the third layer. The first blended region includes aluminum atoms drawn from the first layer into at least the second layer. The semiconductor device further includes a second blended region beneath the second portion of the third layer. The second blended region includes aluminum atoms drawn from the first layer into at least the second layer. The semiconductor device also includes a source contact and a drain contact.
    Type: Application
    Filed: November 3, 2015
    Publication date: March 10, 2016
    Inventors: Chen-Hao CHIANG, Po-Chun LIU, Chi-Ming CHEN, Min-Chang CHING, Chung-Yi YU, Chia-Shiung TSAI, Ru-Liang LEE
  • Semiconductor device, high electron mobility transistor (HEMT) and method of manufacturing
    Patent number: 9245991
    Abstract: A semiconductor device includes a substrate, a channel layer over the substrate, an active layer over the channel layer, and a barrier structure between the substrate and the channel layer. The active layer is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer. The barrier structure is configured to block diffusion of at least one of a material of the substrate or a dopant toward the channel layer.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: January 26, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Chun Liu, Chi-Ming Chen, Chen-Hao Chiang, Chung-Yi Yu, Chia-Shiung Tsai, Xiaomeng Chen
  • Graded aluminum—gallium—nitride and superlattice buffer layer for III-V nitride layer on silicon substrate
    Patent number: 9233844
    Abstract: The present disclosure is directed to an integrated circuit and a method for the fabrication of the integrated circuit. The integrated circuit includes a lattice matching structure. The lattice matching structure can include a first buffer region, a second buffer region and a superlattice structure formed from AlxGa1-xN/AlyGa1-yN layer pairs.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: January 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Ming Chen, Po-Chun Liu, Chung-Yi Yu
  • High electron mobility transistor and method of forming the same
    Patent number: 9236465
    Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A diffusion barrier layer is disposed on top of the second III-V compound layer. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: January 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chun Liu, Chung-Yi Yu, Chi-Ming Chen
  • Method of forming a high electron mobility transistor
    Patent number: 9236464
    Abstract: A method of forming a high electron mobility transistor may include: forming a second III-V compound layer on a first III-V compound layer, the second III-V compound layer and the first III-V compound layer differing in composition; forming a p-type doped region in the first III-V compound layer; forming an n-type doped region in the second III-V compound layer, the n-type doped region overlying the p-type doped region; forming a source feature over the second III-V compound layer, the source feature overlying the n-type doped region; and forming a gate electrode over the second III-V compound layer, the gate electrode disposed laterally adjacent to the source feature.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: January 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hao Chiang, Chi-Ming Chen, Chung-Yi Yu, Po-Chun Liu, Han-Chin Chiu
  • ISOLATION TRENCH THROUGH BACKSIDE OF SUBSTRATE
    Publication number: 20160005642
    Abstract: Among other things, one or more semiconductor arrangements comprising isolation trenches, and techniques for forming such isolation trenches are provided. A substrate comprises a front side surface and a backside surface. One or more devices are formed over the front side surface. A wet etch is performed to form a tapered portion of an isolation trench. A dry etch is performed to form a non-tapered portion of the isolation trench. Because both the wet etch and the dry etch are performed, etching time is reduced compared to merely using the dry etch due to the wet etch having a relatively faster etch rate than the dry etch. In an embodiment, the isolation trench provides isolation for a current leakage path associated with a device or other material formed over the front side surface. In an embodiment, metal is formed within the isolation trench for backside metallization.
    Type: Application
    Filed: September 11, 2015
    Publication date: January 7, 2016
    Inventors: Ming Chyi Liu, Sheng-de Liu, Chi-Ming Chen, Che-Ming Chang, Chung-Yen Chou, Chia-Shiung Tsai
  • High electron mobility transistor and method of forming the same
    Patent number: 9224847
    Abstract: A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is greater than the first band gap. A crystalline interfacial layer is overlying and in contact with the second III-V compound layer. A gate dielectric is over the crystalline interfacial layer. A gate electrode is over the gate dielectric. A source region and a drain region are over the second III-V compound layer, and are on opposite sides of the gate electrode.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Chin Chiu, Po-Chun Liu, Chi-Ming Chen, Chung-Yi Yu, King-Yuen Wong
  • SEMICONDUCTOR STRUCTURE HAVING SETS OF III-V COMPOUND LAYERS AND METHOD OF FORMING THE SAME
    Publication number: 20150349106
    Abstract: A semiconductor structure includes a substrate; and a graded III-V layer over the substrate. The semiconductor structure further includes a p-doped gallium nitride (GaN) layer over the graded III-V layer. The semiconductor structure further includes one or more sets of GaN layers over the p-doped GaN layer. Each set of the one or more sets of GaN layers includes a lower GaN layer, wherein the lower GaN layer is undoped, unintentionally doped having N-type doping, or N-type doped. Each set of the one or more sets of GaN layers includes an upper GaN layer on the lower GaN layer, wherein the upper GaN layer is P-type doped. The semiconductor structure includes a second GaN layer over the one or more sets of GaN layers, the second GaN layer being either undoped or unintentionally doped having the N-type doping. The semiconductor structure includes an active layer over the second GaN layer.
    Type: Application
    Filed: August 12, 2015
    Publication date: December 3, 2015
    Inventors: Chi-Ming CHEN, Po-Chun LIU, Chung-Yi YU, Chia-Shiung TSAI
  • High electron mobility transistor with indium nitride layer
    Patent number: 9202875
    Abstract: A method comprises depositing a first layer comprising aluminum nitride over a substrate. The method further comprises depositing a second layer comprising aluminum gallium nitride over the first layer. The method also comprises depositing a third layer comprising indium gallium nitride over the second layer. The method additionally comprises removing some of the third layer leaving a first portion of the third layer and a second portion of the third layer. The method further comprises reducing an aluminum content of at least the first layer by drawing aluminum atoms from the first layer into at least the second layer beneath the first portion and the second portion of the third layer. The method also comprises depositing a source contact over the first portion of the third layer and a drain contact over the second portion of the third layer.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: December 1, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hao Chiang, Po-Chun Liu, Chi-Ming Chen, Min-Chang Ching, Chung-Yi Yu, Chia-Shiung Tsai, Ru-Liang Lee
  • III-V Multi-Channel FinFETs
    Publication number: 20150340473
    Abstract: A device includes insulation regions over portions of a semiconductor substrate, and a III-V compound semiconductor region over top surfaces of the insulation regions, wherein the III-V compound semiconductor region overlaps a region between opposite sidewalls of the insulation regions. The III-V compound semiconductor region includes a first and a second III-V compound semiconductor layer formed of a first III-V compound semiconductor material having a first band gap, and a third III-V compound semiconductor layer formed of a second III-V compound semiconductor material between the first and the second III-V compound semiconductor layers. The second III-V compound semiconductor material has a second band gap lower than the first band gap. A gate dielectric is formed on a sidewall and a top surface of the III-V compound semiconductor region. A gate electrode is formed over the gate dielectric.
    Type: Application
    Filed: July 31, 2015
    Publication date: November 26, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Ta Lin, Chun-Feng Nieh, Chung-Yi Yu, Chi-Ming Chen
  • Sidewall Passivation for HEMT Devices
    Publication number: 20150318387
    Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.
    Type: Application
    Filed: September 17, 2014
    Publication date: November 5, 2015
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Cheng-Yuan Tsai, Fu-Wei Yao
  • METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    Publication number: 20150287806
    Abstract: A method of making a semiconductor device includes epitaxially growing a channel layer over a substrate. The method further includes depositing an active layer over the channel layer. Additionally, the method includes forming a gate structure over the active layer, the gate structure configured to deplete a 2DEG under the gate structure, the gate structure including a dopant. Furthermore, the method includes forming a barrier layer between the gate structure and the active layer, the barrier layer configured to block diffusion of the dopant from the gate structure into the active layer.
    Type: Application
    Filed: June 22, 2015
    Publication date: October 8, 2015
    Inventors: Po-Chun LIU, Chi-Ming CHEN, Chen-Hao CHIANG, Chung-Yi YU, Chia-Shiung TSAI, Xiaomeng CHEN
  • Reducing wafer distortion through a high CTE layer
    Patent number: 9153435
    Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon (111) surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate. The high CTE layer has a CTE greater than the CTE of silicon. The method includes forming a buffer layer over the second side of the silicon substrate. The buffer layer has a CTE greater than the CTE of silicon. The method includes forming a III-V family layer over the buffer layer. The III-V family layer has a CTE greater than the CTE of the buffer layer.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: October 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Chen, Chung-Yi Yu, Chia-Shiung Tsai, Ho-Yung David Hwang
  • Isolation trench through backside of substrate
    Patent number: 9142614
    Abstract: Among other things, one or more semiconductor arrangements comprising isolation trenches, and techniques for forming such isolation trenches are provided. A substrate comprises a front side surface and a backside surface. One or more devices are formed over the front side surface. A wet etch is performed to form a tapered portion of an isolation trench. A dry etch is performed to form a non-tapered portion of the isolation trench. Because both the wet etch and the dry etch are performed, etching time is reduced compared to merely using the dry etch due to the wet etch having a relatively faster etch rate than the dry etch. In an embodiment, the isolation trench provides isolation for a current leakage path associated with a device or other material formed over the front side surface. In an embodiment, metal is formed within the isolation trench for backside metallization.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: September 22, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ming Chyi Liu, Sheng-de Liu, Chi-Ming Chen, Che-Ming Chang, Chung-Yen Chou, Chia-Shiung Tsa
  • Semiconductor structure having sets of III-V compound layers and method of forming the same
    Patent number: 9142407
    Abstract: A semiconductor structure includes a substrate, a first III-V compound layer over the substrate, one or more sets of III-V compound layers over the first III-V compound layer, a second III-V compound layer over the one or more sets of III-V compound layers, and an active layer over the second III-V compound layer. The first III-V compound layer has a first type doping. Each of the one or more sets of III-V compound layers includes a lower III-V compound layer and an upper III-V compound layer over the lower III-V compound layer. The upper III-V compound layer having the first type doping, and the lower III-V compound layer is at least one of undoped, unintentionally doped having a second type doping, or doped having the second type doping. The second III-V compound layer is either undoped or unintentionally doped having the second type doping.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: September 22, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai
  • CHARGING BRACKET FOR CONSUMER ELECTRONIC PRODUCT
    Publication number: 20150263556
    Abstract: A charging bracket for charging a consumer electronic product includes a first end, a second end, a connecting portion connecting the first end, a second end, a connecting portion, a first connector located at the first end and cooperating with the consumer electronic product, a second connector connecting with the first connector electrically, a coil located on the connecting portion, a wired charging loop comprising the first connector and the second connector and a wireless charging loop comprising the first connector and the coil, wherein the connecting portion is bendable to lie on a plane different from a plane defined by the first end and the second end.
    Type: Application
    Filed: March 11, 2015
    Publication date: September 17, 2015
    Inventors: CHI-MING CHEN, DE-GANG ZHANG, QING WANG
  • Silicon wafer strength enhancement
    Patent number: 9123671
    Abstract: Provided is a method of fabricating a semiconductor device. The method includes: receiving a silicon wafer that contains oxygen; forming a zone in the silicon wafer, the zone being substantially depleted of oxygen; causing a nucleation process to take place in the silicon wafer to form oxygen nuclei in a region of the silicon wafer outside the zone; and growing the oxygen nuclei into defects. Also provided is an apparatus that includes a silicon wafer. The silicon wafer includes: a first portion that is substantially free of oxygen, the first portion being disposed near a surface of the silicon wafer; and a second portion that contains oxygen; wherein the second portion is at least partially surrounded by the first portion.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: September 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Chen, Chung-Yi Yu, Chia-Shiung Tsai, Ho-Yung David Hwang, Alexander Kalnitsky
  • HIGH ELECTRON MOBILITY TRANSISTOR WITH INDIUM NITRIDE LAYER
    Publication number: 20150236101
    Abstract: A method comprises depositing a first layer comprising aluminum nitride over a substrate. The method further comprises depositing a second layer comprising aluminum gallium nitride over the first layer. The method also comprises depositing a third layer comprising indium gallium nitride over the second layer. The method additionally comprises removing some of the third layer leaving a first portion of the third layer and a second portion of the third layer. The method further comprises reducing an aluminum content of at least the first layer by drawing aluminum atoms from the first layer into at least the second layer beneath the first portion and the second portion of the third layer. The method also comprises depositing a source contact over the first portion of the third layer and a drain contact over the second portion of the third layer.
    Type: Application
    Filed: February 18, 2014
    Publication date: August 20, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hao CHIANG, Po-Chun LIU, Chi-Ming CHEN, Min-Chang CHING, Chung-Yi YU, Chia-Shiung TSAI, Ru-Liang LEE
  • HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) HAVING AN INDIUM-CONTAINING LAYER AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20150236146
    Abstract: A high electron mobility transistor (HEMT) includes a substrate, and a channel layer over the substrate, wherein and at least one of the channel layer or the active layer comprises indium. The HEMT further includes an active layer over the channel layer. The active layer has a band gap discontinuity with the channel layer.
    Type: Application
    Filed: February 18, 2014
    Publication date: August 20, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Chun LIU, Chi-Ming CHEN, Min-Chang CHING, Chen-Hao CHIANG, Chung-Yi YU, Chung-Chieh HSU