Patents by Inventor Chi-Ming Chen

Chi-Ming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • III-V multi-channel FinFETs
    Patent number: 9099388
    Abstract: A device includes insulation regions over portions of a semiconductor substrate, and a III-V compound semiconductor region over top surfaces of the insulation regions, wherein the III-V compound semiconductor region overlaps a region between opposite sidewalls of the insulation regions. The III-V compound semiconductor region includes a first and a second III-V compound semiconductor layer formed of a first III-V compound semiconductor material having a first band gap, and a third III-V compound semiconductor layer formed of a second III-V compound semiconductor material between the first and the second III-V compound semiconductor layers. The second III-V compound semiconductor material has a second band gap lower than the first band gap. A gate dielectric is formed on a sidewall and a top surface of the III-V compound semiconductor region. A gate electrode is formed over the gate dielectric.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: August 4, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Ta Lin, Chun-Feng Nieh, Chung-Yi Yu, Chi-Ming Chen
  • Transistor having high breakdown voltage and method of making the same
    Patent number: 9093511
    Abstract: A transistor includes a substrate and a graded layer on the substrate, wherein the graded layer is doped with p-type dopants. The transistor further includes a superlattice layer (SLS) on the graded layer, wherein the SLS has a p-type dopant concentration equal to or greater than 1×1019 ions/cm3. The transistor further includes a buffer layer on the SLS, wherein the buffer layer comprises p-type dopants. The transistor further includes a channel layer on the buffer layer and an active layer on the second portion of the channel layer, wherein the active layer has a band gap discontinuity with the second portion of the channel layer.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: July 28, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai, Xiaomeng Chen
  • SEMICONDUCTOR DEVICE, TRANSISTOR HAVING DOPED SEED LAYER AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20150206962
    Abstract: A semiconductor device includes a substrate, and a seed layer over the substrate, wherein the seed layer comprises carbon dopants. The semiconductor device further includes a channel layer over the seed layer, and an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer. A method of making a transistor includes forming a seed layer over a substrate, and doping the seed layer, wherein doping the seed layer comprises introducing carbon dopants into the seed layer. The method further includes forming a channel layer over the seed layer, and forming an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer.
    Type: Application
    Filed: January 17, 2014
    Publication date: July 23, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Ming CHEN, Po-Chun LIU, Chung-Yi YU, Chia-Shiung TSAI, Ru-Liang LEE
  • Integrated circuit and clock frequency control method of integrated circuit
    Patent number: 9081913
    Abstract: A bus interface includes a chip select terminal, a first transmission bus terminal, a second transmission bus terminal, and a clock control device. The chip select terminal transmits a chip select signal to start the data transmission. When the data transmission starts, the first transmission bus terminal sends data to the second device, and the second transmission bus terminal sends the data from the second device to the first device. The clock control device includes a frequency processing unit and a transmission clock generating unit. The frequency processing unit outputs a clock control signal when a frequency to set value changes. The transmission clock generating unit receives the clock control signal and generates a transmission clock in accordance with the frequency setting value.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: July 14, 2015
    Assignee: Nuvoton Technology Corporation
    Inventor: Chi-Ming Chen
  • Semiconductor device
    Patent number: 9076854
    Abstract: A semiconductor device includes a substrate, a channel layer over the substrate, an active layer over the channel layer, a gate structure over the active layer, and a barrier layer between the gate structure and the active layer. The active layer is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer. The gate structure is configured to deplete the 2DEG under the gate structure. The gate structure includes a dopant. The barrier layer is configured to block diffusion of the dopant from the gate structure into the active layer.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: July 7, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Chun Liu, Chi-Ming Chen, Chen-Hao Chiang, Chung-Yi Yu, Chia-Shiung Tsai, Xiaomeng Chen
  • WIRELESS CHARGER ASSEMBLY MOUNTABLE ON DIFFERENT DESKS
    Publication number: 20150188357
    Abstract: A wireless charger assembly is used for transferring power to an electronic device through inductive charging. The wireless charger assembly includes a bottom case releasably mounted to an exterior flatbed, a transmitter coil, and a top case. The transmitter coil transmits power to a receiver coil of the electronic device through inductive charging. The top case has a working platform mounted around the working surface of the flatbed, a neck portion extending downwardly from the working platform, and a slot defined by the working platform and the neck portion. The neck portion releasably retained to the closed loop wall.
    Type: Application
    Filed: December 29, 2014
    Publication date: July 2, 2015
    Inventors: CHENG-PANG CHEN, YUNG-CHANG CHENG, CHI-MING CHEN, JIA-HONG CHEN
  • WIRELESS CHARGER HAVING MOVEABLE TRANSIMITTER COIL
    Publication number: 20150188356
    Abstract: A wireless charger used for charging a portable electronic device with a receiver coil includes a wireless charging body, a transmitter coil, and a shaft. The charging body has a front body to support the portable electronic device and a rear body coordinated with the front body to form a receiving cavity for receiving transmitter coil. The rear body defines a track for the shaft disposing therein and moving the transmitter coil to align with the receiver coil. The wireless charger could align with receiver coils of different portable electronic devices.
    Type: Application
    Filed: December 29, 2014
    Publication date: July 2, 2015
    Inventors: Cheng-Pang CHEN, Feng ZHOU, Wei REN, Chi-Ming CHEN
  • WIRE-WINDING DEVICE
    Publication number: 20150144728
    Abstract: A wire-winding device comprising: an upper cover; a spiral spring; a rotary base having a groove to accommodate the spiral spring on the bottom surface thereof; a transmission line winding around the rotary base; a lower cover assembled with the upper cover; and a pillar, an outlet, and a wire casing formed on one side of the groove, and two spacers surrounding the peripheral edge of the groove, the pillar having a first end portion which shifts outward to the edge of rotary base, the wire casing having a smooth curved surface formed on the bottom surface thereof near the outlet to enlarge the accommodating space near the outlet and reduce the friction between the transmission line and the spacers.
    Type: Application
    Filed: November 26, 2014
    Publication date: May 28, 2015
    Inventors: CHI-MING CHEN, FENG ZHOU, KAI-FENG YANG
  • WIRE-WINDING DEVICE
    Publication number: 20150144729
    Abstract: A wire-winding device comprising: an upper cover having a bottom surface and a slot deviating from a center of the bottom surface; a rotary base having an annular track on a top surface thereof, the annual track and the slot of the upper cover constituting an orbit; a spiral spring received in the rotary base; a transmission line winding around the rotary base; a lower cover assembled with the upper cover; and an elastic positioning element having a base and a positioning part extruding from the lower surface of the base, the base having an elastic part and a respective fixed part at each of two ends thereof, the elastic positioning element being moveable along the orbit in response to a rotational movement of the rotary base to avoid the transmission line to be tied a knot.
    Type: Application
    Filed: November 26, 2014
    Publication date: May 28, 2015
    Inventors: CHI-MING CHEN, KAI-FENG YANG
  • METHOD OF FORMING A HIGH ELECTRON MOBILITY TRANSISTOR
    Publication number: 20150087118
    Abstract: A method of forming a high electron mobility transistor may include: forming a second III-V compound layer on a first III-V compound layer, the second III-V compound layer and the first III-V compound layer differing in composition; forming a p-type doped region in the first III-V compound layer; forming an n-type doped region in the second III-V compound layer, the n-type doped region overlying the p-type doped region; forming a source feature over the second III-V compound layer, the source feature overlying the n-type doped region; and forming a gate electrode over the second III-V compound layer, the gate electrode disposed laterally adjacent to the source feature.
    Type: Application
    Filed: November 20, 2014
    Publication date: March 26, 2015
    Inventors: Chen-Hao Chiang, Chi-Ming Chen, Chung-Yi Yu, Po-Chun Liu, Han-Chin Chiu
  • LOCK STRUCTURE
    Publication number: 20150069769
    Abstract: A lock structure includes a first mounting plate and a positioning ring. The first mounting plate comprises a bottom plate and a plurality of fixing holes. The positioning ring comprises a ring body, an opening and a plurality of positioning members, and each of the positioning members comprises a positioning barrel having a body and a penetration hole. Each of the penetration holes is surrounded by each of the bodies. Each of the penetration holes corresponds to each of the fixing holes to make a fixing member passing through the fixing hole and fixedly secured at a positioning rod via guidance of each of the penetration holes. Therefore, the difficulty of assembly caused by the reason the fixing member is unable to align with the positioning member is eliminated.
    Type: Application
    Filed: February 18, 2014
    Publication date: March 12, 2015
    Applicant: TAIWAN FU HSING INDUSTRIAL CO., LTD.
    Inventor: Chi-Ming Chen
  • Electrical connector assembly and method of manufacturing the same
    Patent number: 8974251
    Abstract: An electrical connector assembly comprises: a metallic housing having a receiving space extending along a longitudinal and two openings respectively formed on top and bottom surfaces thereof and communicated with the receiving space; a pair of flexible printed circuit boards (FPCs) received into the receiving space and arranged in a back-to-back manner. Each of the FPC defines a protuberant portion extending into the corresponding opening. And each of the protuberant portion has a plurality of contacts formed on one side thereof and communicated with an exterior. A pair of supporting pieces are received into the receiving space and attached to another side of the protuberant portion. And a spacer is received into the receiving space and sandwiched between the pair of flexible printed circuit boards and supporting pieces.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: March 10, 2015
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Jun Zong, Chi-Ming Chen
  • Transistor having an ohmic contact by gradient layer and method of making the same
    Patent number: 8975641
    Abstract: A transistor includes a substrate, a channel layer over the substrate and an active layer over the channel layer. The active layer includes a gradient having a first concentration of a first material at an interface with the channel layer and a second concentration of the first material at a surface opposite the channel layer, and the first concentration is higher than the second concentration.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hao Chiang, Po-Chun Liu, Chi-Ming Chen, Chung-Yi Yu, Chia-Shiung Tsai, Xiaomeng Chen
  • Transistor having an ohmic contact by screen layer and method of making the same
    Patent number: 8969882
    Abstract: A transistor includes a substrate, a channel layer over the substrate and an active layer over the channel layer. The active layer includes a first portion and a screen layer over the first portion. The transistor includes a metal layer over the screen layer.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hao Chiang, Po-Chun Liu, Chi-Ming Chen, Chung-Yi Yu, Chia-Shiung Tsai, Xiaomeng Chen
  • TRANSISTOR HAVING AN OHMIC CONTACT BY SCREEN LAYER AND METHOD OF MAKING THE SAME
    Publication number: 20150053990
    Abstract: A transistor includes a substrate, a channel layer over the substrate and an active layer over the channel layer. The active layer includes a first portion and a screen layer over the first portion. The transistor includes a metal layer over the screen layer.
    Type: Application
    Filed: August 26, 2013
    Publication date: February 26, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hao CHIANG, Po-Chun LIU, Chi-Ming CHEN, Chung-Yi YU, Chia-Shiung TSAI, Xiaomeng CHEN
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING
    Publication number: 20150053992
    Abstract: A semiconductor device includes a substrate, a channel layer over the substrate, an active layer over the channel layer, a gate structure over the active layer, and a barrier layer between the gate structure and the active layer. The active layer is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer. The gate structure is configured to deplete the 2DEG under the gate structure. The gate structure includes a dopant. The barrier layer is configured to block diffusion of the dopant from the gate structure into the active layer.
    Type: Application
    Filed: August 26, 2013
    Publication date: February 26, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Chun LIU, Chi-Ming CHEN, Chen-Hao CHIANG, Chung-Yi YU, Chia-Shiung TSAI, Xiaomeng CHEN
  • TRANSISTOR HAVING AN OHMIC CONTACT BY GRADIENT LAYER AND METHOD OF MAKING THE SAME
    Publication number: 20150053991
    Abstract: A transistor includes a substrate, a channel layer over the substrate and an active layer over the channel layer. The active layer includes a gradient having a first concentration of a first material at an interface with the channel layer and a second concentration of the first material at a surface opposite the channel layer, and the first concentration is higher than the second concentration.
    Type: Application
    Filed: August 26, 2013
    Publication date: February 26, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hao CHIANG, Po-Chun LIU, Chi-Ming CHEN, Chung-Yi YU, Chia-Shiung TSAI, Xiaomeng CHEN
  • SEMICONDUCTOR DEVICE, HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) AND METHOD OF MANUFACTURING
    Publication number: 20150041825
    Abstract: A semiconductor device includes a substrate, a channel layer over the substrate, an active layer over the channel layer, and a barrier structure between the substrate and the channel layer. The active layer is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer. The barrier structure is configured to block diffusion of at least one of a material of the substrate or a dopant toward the channel layer.
    Type: Application
    Filed: August 12, 2013
    Publication date: February 12, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Chun LIU, Chi-Ming CHEN, Chen-Hao CHIANG, Chung-Yi YU, Chia-Shiung TSAI, Xiaomeng CHEN
  • High Electron Mobility Transistor and Method of Forming the Same
    Publication number: 20150021667
    Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A diffusion barrier layer is disposed on top of the second III-V compound layer. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode.
    Type: Application
    Filed: October 10, 2014
    Publication date: January 22, 2015
    Inventors: Po-Chun Liu, Chung-Yi Yu, Chi-Ming Chen
  • TRANSISTOR HAVING PARTIALLY OR WHOLLY REPLACED SUBSTRATE AND METHOD OF MAKING THE SAME
    Publication number: 20150021666
    Abstract: A transistor includes a substrate, a channel layer over the substrate, an active structure over the channel layer, a gate electrode over the channel layer, and a drain electrode over the channel layer. The active structure is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active structure. The gate electrode and the drain electrode define a first space therebetween. The substrate has a first portion directly under the first space defined between the gate electrode and the drain electrode, and the first portion has a first electrical conductivity value less than that of intrinsic silicon and a thermal conductivity value greater than that of intrinsic silicon.
    Type: Application
    Filed: July 17, 2013
    Publication date: January 22, 2015
    Inventors: Chi-Ming CHEN, Chih-Wen HSIUNG, Yuan-Chih HSIEH, Po-Chun LIU, Ming Chyi LIU, Chung-Yi YU, Chia-Shiung TSAI, Xiaomeng CHEN