Abstract: Among other things, one or more semiconductor arrangements comprising isolation trenches, and techniques for forming such isolation trenches are provided. A substrate comprises a front side surface and a backside surface. One or more devices are formed over the front side surface. A wet etch is performed to form a tapered portion of an isolation trench. A dry etch is performed to form a non-tapered portion of the isolation trench. Because both the wet etch and the dry etch are performed, etching time is reduced compared to merely using the dry etch due to the wet etch having a relatively faster etch rate than the dry etch. In an embodiment, the isolation trench provides isolation for a current leakage path associated with a device or other material formed over the front side surface. In an embodiment, metal is formed within the isolation trench for backside metallization.

Abstract: A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is smaller than the first band gap. The HEMT further includes a third III-V compound layer having a third band gap over the second III-V compound layer, wherein the third band gap is greater than the first band gap. A gate electrode is formed over the third III-V compound layer. A source region and a drain region are over the third III-V compound layer and on opposite sides of the gate electrode.

Abstract: An electronic device includes an input power detection unit, a transmission control unit and a converter. The input power detection unit is configured to determine an input voltage value and an input current value of an input power. In response to the input power, the transmission control unit is configured to determine a first voltage value and a first current value associated with another electronic device via a handshake process. The voltage converter is configured to convert the input power into a first power required by the another electronic device.

Abstract: The present disclosure relates to a transistor device having a donor bi-layer configured to provide low-resistance to source and drain contacts while maintaining a high-mobility two-dimensional electron gas within a channel layer, and an associated method of formation. In some embodiments, the transistor device has a channel layer disposed over a substrate and a donor bi-layer disposed over the channel layer. The donor bi-layer includes a mobility-enhancing layer of AlzGa(1-z)N disposed over the channel layer and having a first molar fraction z in a first range, and a resistance-reducing layer of AlxGa(1-x)N disposed on and in contact with the mobility-enhancing layer of AlzGa(1-z)N and having a second molar fraction x in a second range less than the first range. Source and drain contacts are over the resistance-reducing layer of AlxGa(1-x)N. The donor bi-layer has a conduction band energy that monotonically decreases from top to bottom surfaces of the donor bi-layer.

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

Abstract: An electronic device includes a voltage converter configured to provide an output having an output voltage value and an output current value. The electronic device also includes a handshake control unit a handshake control unit, coupled to the voltage converter, configured to perform a handshake process for a charging voltage value and receive a matching result of the handshake process. The electronic device further includes a matching management unit, coupled to the handshake control unit, configured to send a first request for resuming matching to the handshake control unit in response to the matching result as being failed.

Abstract: The present disclosure relates to a structure and method of forming a GaN film on a Si substrate that includes an additional or second high temperature (HT) AlN seed layer, introduced for reducing the tensile stress of GaN on a Si substrate. The second HT AlN seed layer is disposed over a first HT AlN seed layer, and has a low V/III ratio compared to the first HT AlN seed layer. The second HT AlN seed layer has better lattice matching between Si and GaN and this reduces the tensile stress on GaN. The additional HT AlN seed layer further acts as a capping layer and helps annihilate or terminate threading dislocations (TDs) originating from a LT AlN seed layer. The second HT AlN seed layer also helps prevent Si diffusion from the substrate to the GaN film.

Abstract: A method of making a semiconductor device includes epitaxially growing a channel layer over a substrate. The method further includes depositing an active layer over the channel layer. Additionally, the method includes forming a gate structure over the active layer, the gate structure configured to deplete a 2DEG under the gate structure, the gate structure including a dopant. Furthermore, the method includes forming a barrier layer between the gate structure and the active layer, the barrier layer configured to block diffusion of the dopant from the gate structure into the active layer.

Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A dielectric passivation layer is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer, and extend through the dielectric passivation layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. The gate electrode has an exterior surface. An oxygen containing region is embedded at least in the second III-V compound layer under the gate electrode. A gate dielectric layer has a first portion and a second portion. The first portion is under the gate electrode and on the oxygen containing region. The second portion is on a portion of the exterior surface of the gate electrode.

Abstract: A cable connector assembly includes an insulative housing, an upper and a lower row of contacts received by the insulative housing, a printed circuit board assembled on a rear end of the insulative housing and electrically connected with the contacts, a shielding case enclosing the insulative housing; and a cable connected with a rear end of the printed circuit board, wherein the insulative housing includes a main body, a tongue portion positioned on a front end of the main body, and a front end portion separately molded on the tongue portion and on a front end of the contacts, and each of the upper and the lower row of contacts defines a contacting portion projecting outwardly, a fixing portion interference fitted with tongue portion, a tail portion electrically connected with the printed circuit board and a bent portion connected between the fixing portion and the tail portion.

Abstract: A semiconductor device includes an indium gallium nitride layer over an active layer. The semiconductor device further includes an annealed region beneath the indium gallium nitride layer, the annealed region comprising indium atoms driven from the indium gallium nitride layer into the active layer.

Abstract: A transistor includes a substrate and a buffer layer on the substrate, wherein the buffer layer comprises p-type dopants. The transistor further includes a channel layer on the buffer layer and a back-barrier layer between a first portion of the channel layer and a second portion of the channel layer. The back-barrier layer has a band gap discontinuity with the channel layer. The transistor further includes an active layer on the second portion of the channel layer, wherein the active layer has a band gap discontinuity with the second portion of the channel layer. The transistor further includes a two dimensional electron gas (2-DEG) in the channel layer adjacent an interface between the channel layer and the active layer.

Abstract: A cable connector assembly (100) comprises: a first connector (10) having a main body (120), a number of contacts (121) retained in the main body, a first circuit board (130) electrically connected to the contacts, and a metal shell (110) enclosing the first circuit board; a cable (30) electrically connected between the first circuit board and a power source to provide a power to the first circuit board; a second circuit board (150) vertically fixed on the metal shell; a cover enclosing the first and the second circuit board; a luminous element (152) disposed on a front side of the second circuit board and electrically connected to the first circuit board; and a translucent portion (1610) defined on a front end of the cover to pass light emitted by the luminous element.

Abstract: The present disclosure relates to a donor layer of bi-layer AlGaN and associated method of fabrication within a high electron mobility transistor (HEMT) configured to provide low-resistance ohmic source and drain contacts to reduce power consumption, while maintaining a high-mobility of a two-dimensional electron gas (2DEG) within a channel of the HEMT. The donor layer of bi-layer AlGaN comprises a mobility-enhancing layer of AlzGa(1-z)N, a resistance-reducing layer of AlxGa(1-x)N disposed over the mobility-enhancing layer, wherein the ohmic source and drain contacts connect to the HEMT. A channel layer of GaN is disposed beneath the mobility-enhancing layer, wherein a 2DEG resides, forming the channel of the HEMT.

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

Abstract: A transistor with a multi-strained layer superlattice (SLS) structure is provided. A first strained layer superlattice (SLS) layer is arranged over a substrate. A first buffer layer is arranged over the first SLS layer and includes dopants configured to increase a resistance of the first buffer layer. A second SLS layer is arranged over the first buffer layer. A second buffer layer is arranged over the second SLS layer and includes dopants configured to increase a resistance of the second buffer layer. A channel layer is arranged over the second buffer layer. An active layer is arranged over and directly abuts the channel layer. The channel and active layers collectively define a heterojunction. A method for manufacturing the transistor is also provided.

Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A dielectric passivation layer is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer, and extend through the dielectric passivation layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. The gate electrode has an exterior surface. An oxygen containing region is embedded at least in the second III-V compound layer under the gate electrode. A gate dielectric layer has a first portion and a second portion. The first portion is under the gate electrode and on the oxygen containing region. The second portion is on a portion of the exterior surface of the gate electrode.

Abstract: A semiconductor device includes a substrate, a first layer over the substrate, a second layer over the first layer, and a third layer over the second layer. The third layer has a first portion and a second portion. The first portion of the third layer is separated from the second portion of the third layer. The semiconductor device also includes a first blended region beneath the first portion of the third layer. The first blended region includes aluminum atoms drawn from the first layer into at least the second layer. The semiconductor device further includes a second blended region beneath the second portion of the third layer. The second blended region includes aluminum atoms drawn from the first layer into at least the second layer. The semiconductor device also includes a source contact and a drain contact.

Abstract: A cable connector assembly (100) includes: a cable (30) having a number of inner wires; a first connector (10) including a main body (120), plural contacts (121) retained in the main body, a first circuit board (130), a luminous element (152), and a cover; and a second circuit board (180) assembled on a rear end of the first circuit board and getting power and grounding source from the first circuit board. The second circuit board includes a detection contact (182) electrically connected to an inner wire of the cable, and a chip (181) electrically connected respectively to the luminous element and the detection contact. The chip detects a voltage difference between the power source and the first connector. A light is emitted by the luminous element passing through the cover to indicate a charging status of the charging device.

Abstract: A cable connector assembly (100) comprises: a first connector (10) having a main body (120), a number of contacts (121) retained in the main body, a first circuit board (130) electrically connected to the contacts, and a metal shell (110) enclosing the first circuit board; a cable (30) electrically connected between the first circuit board and a power source to provide a power to the first circuit board; a second circuit board (150) vertically fixed on the metal shell; a cover enclosing the first and the second circuit board; a luminous element (152) disposed on a front side of the second circuit board and electrically connected to the first circuit board; and a translucent portion (1610) defined on a front end of the cover to pass light emitted by the luminous element.