Patents by Inventor Chi-Sun Hwang

Chi-Sun Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Level shifter circuit
    Patent number: 9628079
    Abstract: A level shifter circuit a first transistor connected between a power source terminal of the level shifter circuit and an output terminal of the level shifter circuit, the first transistor being configured to transmit, in response to a first signal and a second signal, a power source voltage applied from the power source terminal to the output terminal, the first signal being received from an input terminal of the level shifter circuit through a first gate of the first transistor, the second signal being received through a second gate of the first transistor, and a second transistor connected between a ground terminal of the level shifter circuit and the output terminal, the second transistor being configured to transmit a ground voltage from the ground terminal to the output terminal in response to a gate signal received through a gate of the second transistor.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: April 18, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jae-Eun Pi, Chunwon Byun, OhSang Kwon, Eunsuk Park, Min Ki Ryu, Chi-Sun Hwang
  • Display device, method of fabricating the same, and method of fabricating image sensor device
    Patent number: 9613984
    Abstract: Provided are a display device, a method of fabricating the display device, and a method of fabricating an image sensor device. The method of fabricating the display device includes preparing a substrate including a cell array area and a peripheral circuit area, forming a silicon layer on the peripheral circuit area of the substrate, forming oxide layers on the cell array area and the peripheral circuit area of the substrate, forming gate dielectric layers on the silicon layer and the oxide layers, forming the gate electrodes on the gate dielectric layers, wherein the gate electrodes expose both ends of the silicon layer and both ends of the oxide layers, and injecting dopant into both ends of the silicon layer and both ends of the oxide layers at the same time.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: April 4, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jong-Heon Yang, Jonghyurk Park, Chunwon Byun, Chi-Sun Hwang
  • Electrochromic device
    Patent number: 9581876
    Abstract: Provided is an electrochromic device and a method for driving the electrochromic device, the electrochromic device including a first electrode, a first electrochromic layer, an electrolyte layer, a second electrochromic layer, and a second electrode which are laminated in sequence, at least one selected from among the group consisting of the first and second electrochromic layers and the electrolyte layer including scattering particles, and the electrochromic device further including an additional layer that contains the scattering particles and is disposed between the electrolyte layer and the first or second electrochromic layer.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: February 28, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Seong-Mok Cho, Joo Yeon Kim, Tae-Youb Kim, Hojun Ryu, Chil Seong Ah, Sang Hoon Cheon, Yong Hae Kim, Juhee Song, Chi-Sun Hwang
  • GATE DRIVING CIRCUIT AND ORGANIC LIGHT EMITTING DISPLAY DEVICE INCLUDING THE SAME
    Publication number: 20170032741
    Abstract: Provided is a gate driving circuit. The gate driving circuit includes an ith modulation circuit and an ith line selection circuit (where i is a natural number greater than 1). The ith modulation circuit outputs an ith modulation voltage to an ith line selection circuit based on received first to third control signals. The ith line selection circuit includes a memory transistor that is turned on or turned off according to a level of the received ith modulation voltage.
    Type: Application
    Filed: July 27, 2016
    Publication date: February 2, 2017
    Inventors: Chunwon BYUN, Jong-Heon YANG, Sung-Min YOON, Kyoung Ik CHO, Chi-Sun HWANG
  • Display device and method of manufacturing the same
    Patent number: 9535283
    Abstract: Provided is a display device and a method of manufacturing the same. The display device includes a reflective display part including a first cathode electrode and a first anode electrode and a liquid crystal layer, a light emitting display part including a second cathode electrode and a second anode electrode and a light emission film, and a thin film transistor part being electrically connected to the first and second anode electrodes. The light emitting display part further includes a bank disposed on one side of the second anode electrode between the second anode electrode and the light emission film.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: January 3, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yong Hae Kim, Gi Heon Kim, Hojun Ryu, Chi-Sun Hwang, Jong-Heon Yang, Sang Chul Lim, Jae Bon Koo, Jonghee Lee, Jeong Ik Lee
  • DISPLAY PANEL AND DISPLAY DEVICE INCLUDING THE SAME
    Publication number: 20160267827
    Abstract: A display panel includes pixels connected to each of gate lines and data lines. Each of the pixels includes a first transistor connected between a corresponding data line among the data lines and a first node and configured to deliver a data signal of the corresponding data line to the first node in response to an input signal received through a corresponding gate line among the gate lines, a reflective element circuit connected to the first node, and configured to implement the reflective mode in response to a signal of the first node when a first mode selection signal indicates a reflective mode, an emissive element circuit connected to a second node, and configured to implement the emissive mode in response to the signal of the first node when the mode selection mode indicates an emissive mode.
    Type: Application
    Filed: January 27, 2016
    Publication date: September 15, 2016
    Inventors: Chunwon BYUN, Jae-Eun PI, Kyoung Ik CHO, Hye Yong CHU, Chi-Sun HWANG
  • LEVEL SHIFTER CIRCUIT
    Publication number: 20160248426
    Abstract: A level shifter circuit a first transistor connected between a power source terminal of the level shifter circuit and an output terminal of the level shifter circuit, the first transistor being configured to transmit, in response to a first signal and a second signal, a power source voltage applied from the power source terminal to the output terminal, the first signal being received from an input terminal of the level shifter circuit through a first gate of the first transistor, the second signal being received through a second gate of the first transistor, and a second transistor connected between a ground terminal of the level shifter circuit and the output terminal, the second transistor being configured to transmit a ground voltage from the ground terminal to the output terminal in response to a gate signal received through a gate of the second transistor.
    Type: Application
    Filed: February 22, 2016
    Publication date: August 25, 2016
    Inventors: Jae-Eun PI, Chunwon BYUN, OhSang KWON, Eunsuk PARK, Min Ki RYU, Chi-Sun HWANG
  • DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME
    Publication number: 20160246116
    Abstract: Provided is a display device. The display device includes a lower display element where a substrate, a first lower electrode, a liquid crystal part, and a second lower electrode are sequentially stacked, an upper display element stacked vertical to the lower display element, where a first upper electrode, a light emitting part, a second upper electrode, and a protective part are sequentially stacked, and a middle part configured to deliver a driving signal to the lower and upper display elements, between the lower and upper display elements.
    Type: Application
    Filed: January 29, 2016
    Publication date: August 25, 2016
    Inventors: Jong-Heon YANG, Jae Bon KOO, Byoung-Hwa KWON, Gi Heon KIM, Yong Hae KIM, Hojun RYU, Chan Woo PARK, Chunwon BYUN, Hyunkoo LEE, Jong Tae LIM, Kyoung Ik CHO, Seong-Mok CHO, Hye Yong CHU, Chi-Sun HWANG
  • SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    Publication number: 20160240563
    Abstract: Provided is a semiconductor device. The semiconductor device includes a second semiconductor pattern disposed on the substrate and configured to provide a channel region, and a first semiconductor pattern disposed between the substrate and the second semiconductor pattern, wherein the first semiconductor pattern includes a channel region that is a portion in contact with the second semiconductor pattern and source/drain regions that are portions exposed by the second semiconductor pattern.
    Type: Application
    Filed: February 12, 2016
    Publication date: August 18, 2016
    Inventors: Sang-Hee PARK, Chi-Sun HWANG, Min Ki RYU, Jae-Eun PI, Jong-Beom KO, Hyein YEOM
  • HOLOGRAPHIC DISPLAY DEVICE
    Publication number: 20160209809
    Abstract: Provided is a holographic display device. The holographic display device includes a light source unit configured to emit a light, and a spatial light modulator (SLM) configured to modulate at least one of a phase and amplitude of the light emitted from the light source unit to output a hologram image, and including a plurality of pixel groups that are arranged in a first direction, wherein each of the plurality of pixel groups includes: first pixels arranged in a matrix x1×y1 and providing an image having a first wavelength, and second pixels adjacent to the first pixels in the first direction, arranged in a matrix x2×y2, and providing an image having a second wavelength that is different from the first wavelength.
    Type: Application
    Filed: January 12, 2016
    Publication date: July 21, 2016
    Inventors: Yong Hae Kim, Chi-Sun Hwang, Gi Heon Kim, Himchan Oh, Hojun Ryu, Chunwon Byun, Myung Lae Lee, Jae Won Lee, Jae-Eun Pi
  • HOLOGRAPHIC DISPLAY APPARATUS AND METHOD OF DRIVING THE SAME
    Publication number: 20160209808
    Abstract: A holographic display apparatus includes a light source unit, a spatial light modulator, and a spatial light modulator control circuit for controlling the spatial light modulator, the spatial light modulator control circuit including a data driving circuit for providing a data voltage to a signal line, a demultiplexer circuit which includes a plurality of switching elements connected to the signal line and sequentially turned on, and transfers the data voltage to a transfer line through a turned-on switching element among the switching elements, and a first element connected between the transfer line and a data line, passing a current flowing from the transfer line to the data line, and blocking a current flowing from the data line to the transfer line.
    Type: Application
    Filed: January 15, 2016
    Publication date: July 21, 2016
    Inventors: Chunwon BYUN, Jae-Eun PI, Yong Hae KIM, HAKYUN LEE, Chi-Sun HWANG
  • Dual mode display apparatus and method of manufacturing the same
    Patent number: 9379350
    Abstract: A dual mode display apparatus according to the inventive concept includes a lower substrate, a first lower electrode on the lower substrate, a light switching layer on the first lower electrode, a first upper electrode on the light switching layer, a passivation layer on the first upper electrode, a contact plug connected to the first upper electrode and penetrating the passivation layer, a second lower electrode on the contact plug and the passivation layer, an organic light-emitting layer on the second lower electrode, a second upper electrode on the organic light-emitting layer, and an upper substrate on the second upper electrode.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: June 28, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jae Bon Koo, Hojun Ryu, Chi-Sun Hwang, Jeong Ik Lee, Hye Yong Chu
  • SELF-ALIGNED THIN FILM TRANSISTOR AND FABRICATION METHOD THEREOF
    Publication number: 20160104804
    Abstract: Disclosed are a self-aligned thin film transistor capable of simultaneously improving an operation speed and stability and minimizing a size thereof by forming source and drain electrodes so as to be self-aligned, and a fabrication method thereof. The method of fabricating a thin film transistor according to an exemplary embodiment of the present disclosure includes: forming an active layer, a gate insulator, and a gate layer on a substrate; forming a photoresist layer pattern for defining a shape of a gate electrode on the gate layer; etching the gate layer, the gate insulator, and the active layer by using the photoresist layer pattern; depositing a source and drain layer on the etched substrate by a deposition method having directionality; and forming a gate electrode and self-aligned source electrode and drain electrode by removing the photoresist layer pattern.
    Type: Application
    Filed: December 16, 2015
    Publication date: April 14, 2016
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Him Chan OH, Chi Sun HWANG, Sang Hee PARK
  • Dual display device with vertical structure
    Patent number: 9299758
    Abstract: Disclosed is a dual display device having a vertical structure, in which a reflective display device and a self-emissive display device are formed on one substrate in a vertical structure so as to enable a reflective display or a self-emissive display according to a situation and provide a high resolution display. The dual display device having a vertical structure includes: a thin film transistor formed on a substrate; a white light emitting device formed on the thin film transistor: a reflection adjusting layer formed on the white light emitting device; and a color converting layer formed on the reflection adjusting layer.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: March 29, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sang Hee Park, Chi Sun Hwang
  • Oxide transistor with nano-layered structure
    Patent number: 9263592
    Abstract: A transistor includes source/drain electrodes provided on a substrate; a semiconductor oxide layer provided between the source/drain electrodes; a gate electrode facing the semiconductor oxide layer; and a gate insulating layer interposed between the semiconductor oxide layer and the gate electrode, wherein the semiconductor oxide layer has a nano-layered structure including at least one first nano layer comprised of a first material and at least one second nano layer comprised of a second material that are alternatingly stacked one on another to provide at least one interface, and wherein the first material and the second material are different materials that are effective to form an electron transfer channel layer at the interface.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: February 16, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Su Jae Lee, Chi-Sun Hwang, Hye Yong Chu, Sang Chul Lim, Jae-Eun Pi, Min Ki Ryu
  • Transistor and method of fabricating the same
    Patent number: 9252222
    Abstract: Provided is a transistor. The transistor includes: a substrate; a semiconductor layer provided on the substrate and having one side vertical to the substrate and the other side facing the one side; a first electrode extending along the substrate and contacting the one side of the semiconductor layer; a second electrode extending along the substrate and contacting the other side of the semiconductor layer; a conductive wire disposed on the first electrode and spaced from the second electrode; a gate electrode provided on the semiconductor layer; and a gate insulating layer disposed between the semiconductor layer and the gate electrode, wherein the semiconductor layer, the first electrode, and the second electrode have a coplanar.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: February 2, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung Haeng Cho, Sang-Hee Park, Chi-Sun Hwang
  • Self-aligned thin film transistor and fabrication method thereof
    Patent number: 9252241
    Abstract: Disclosed are a self-aligned thin film transistor capable of simultaneously improving an operation speed and stability and minimizing a size thereof by forming source and drain electrodes so as to be self-aligned, and a fabrication method thereof. The method of fabricating a thin film transistor according to an exemplary embodiment of the present disclosure includes: forming an active layer, a gate insulator, and a gate layer on a substrate; forming a photoresist layer pattern for defining a shape of a gate electrode on the gate layer; etching the gate layer, the gate insulator, and the active layer by using the photoresist layer pattern; depositing a source and drain layer on the etched substrate by a deposition method having directionality; and forming a gate electrode and self-aligned source electrode and drain electrode by removing the photoresist layer pattern.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: February 2, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Him Chan Oh, Chi Sun Hwang, Sang Hee Park
  • Self-aligned thin film transistor with doping barrier and method of manufacturing the same
    Patent number: 9245978
    Abstract: Disclosed are a self-aligned thin film transistor controlling a diffusion length of a doping material using a doping barrier in a thin film transistor having a self-aligned structure and a method of manufacturing the same. The self-aligned thin film transistor with a doping barrier includes: an active layer formed on a substrate and having a first doping region, a second doping region, and a channel region; a gate insulating film formed on the channel region; a gate electrode formed on the gate insulating film; a doping source film formed on the first doping region and the second doping region; and a doping barrier formed between the doping source film and the first doping region and between the doping source film and the second doping region.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: January 26, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Chi Sun Hwang, Sang Hee Park, Him Chan Oh
  • Dual-mode display device and method of manufacturing same
    Patent number: 9236577
    Abstract: Provided are a dual-mode display device and a method of manufacturing the same. The device includes a lower substrate, an upper substrate facing the lower substrate, a thin-film transistor portion between the upper substrate and the lower substrate, a first anode on one side of the thin-film transistor portion, a first cathode between the first anode and the upper substrate, an organic light-emitting layer between the first cathode and the first anode, a second anode on the other side of the thin-film transistor portion, a second cathode between the second anode and the upper substrate, or the second anode and the lower substrate, and a optical switching layer between the second cathode and the second anode.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: January 12, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jae Bon Koo, Jeong Ik Lee, Chi-Sun Hwang, Hojun Ryu, Hye Yong Chu
  • Display device and method of driving the same
    Patent number: 9236006
    Abstract: Provided is a display device. The display device includes: a pixel including an emissive element circuit, a reflective element circuit, and a switch transistor selecting one of the emissive element circuit and the reflective element circuit; an illumination sensor generating an illumination information signal according to an illumination of an external light source by detecting the external light source; and a controller generating control signals for driving the pixel according to pixel data, wherein the controller generates a light signal controlling the switch transistor by referencing the illumination information signal.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: January 12, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hyunkoo Lee, Jae-Eun Pi, Chi-Sun Hwang, Jong-Heon Yang