Abstract: The present invention provides a $ for canceling DC offset, comprising: a first circuit accumulating a first square value of a plurality of signal values in a time period; a second circuit calculation a second square value of an accumulation of said signal values in said time period, wherein said square value is divided by a quantity of said signal values in said time period to generate a DC offset value; and a third circuit, connected to said first circuit and second circuit, calculating a difference between said first square value and said DC offset value.

Abstract: A method for estimating the signal quality of a communication channel is disclosed. Firstly, an input signal passes through a match filter at the initial stage of an estimation period. Next, the output of the match filter is calculated to obtain the noise reference value within a pre-determined period. The output value of the match filter and the noise reference value are compared. When the output value of the match filter is larger than the noise reference value, a valid power value is obtained according to the output value of the match filter. The valid power values are accumulated. Finally, a SNR is calculated according to the noise reference value and the accumulated valid power value at the end of the estimation period. Thereby, the signal quality of the wireless communication channel is estimated according to the SNR, and the signal transmission rate is determined.

Abstract: A method for loading configuration data onto a non-volatile memory and the device using the same is provided. A non-volatile memory block is preloaded with a certain compatible memory configuration data in advance when the memory device is being manufactured. The memory configuration data comprises plural parameters corresponding to the non-volatile memory. When readying the memory device, the preloaded configuration data is loaded onto a random-access memory thereof so as to save the space in a read-only memory used for storing the memory's identification and its specification. Additionally, means for loading the configuration data from the preload zone onto the random-access memory is introduced to update the firmware.

Abstract: A memory storage device and a read/write method thereof, first defining logically the flash memory as at least one particular data management area and at least one common data management area; next, determining the logical block address located in the particular data management area or the common data management area according to data transmitted to an external system by an area decision mechanism, wherein the method of writing to the particular data management area is by using a method of dynamic deviation value, and the method of writing to the common data management area is by using a method of same displacement value. Whereby, the particular data management area can be avoided moving frequently caused by updating data from the external system to improve read/write performance of the flash memory.

Abstract: Computing an angle between a real part and an imaginary part of a complex number includes receiving complex number data; generating a first value, a second value and a determination result according to the complex number data; choosing a dividend and a divisor of a division operation from the first value and the second value for generating a division result according to magnitudes of the first value and the second value; performing table look-up for the division result to generate a table look-up result according to a preserved table; and adjusting the table look-up result for generating an angle corresponding to the complex number data according to the determination result.

Abstract: A frequency synthesizer applied to a digital television tuner includes: a voltage controlled oscillator (VCO), a phase locked loop (PLL), a frequency divider unit, and a multiplexer. The maximum oscillated frequency of the VCO is twice its minimum frequency. The PLL controls and locks the VCO output frequency by a frequency control signal. The frequency divider unit includes a plurality of first dividers which form a cascade connection. The frequency divider unit receives the VCO output frequency, and subsequently divides the output frequency one by one. The multiplexer receives the dividing signals, and then chooses one of the dividing signals by a frequency selection signal, and generates a local oscillation signal. Hence, the present invention can implement the frequency synthesizer by simple architecture and cover the frequency ranges of Digital Video Broadcasting standard.

Abstract: A card reader that can enhance the efficiency of the application system is embedded in the application system. The application system has an external memory drive. The card reader includes at least one memory card connector, a flash memory, and a control unit. The memory card connector is used for being plugged with a memory card. The flash memory is driven and integrated by the external memory drive. The control unit is electrically connected with the memory card connector and the flash memory and is used for transmitting data between the memory card and the flash memory and the application system via the control unit. Thereby, the flash memory can be used as an extended memory of the application system. The total memory of the application system increases, and the efficiency of the application system is enhanced.

Abstract: An assessment system classifies a plurality of channels to several channel groups according to the characteristics of the channel groups and assesses the status of each channel by a corresponding method, such as a period comparison method or a SNR comparison method, defined based on the channel groups. Hence, the present invention allows simpler computations to be made and a simpler circuit structure to be used.

Abstract: A packet detecting circuit detects a packet inputting time via calculating a delay correlation function and an autocorrelation function. In order to prevent a DC offset from affecting the calculation of the delay correlation function and the autocorrelation function, when the packet detecting circuit calculates the delay correlation function and the autocorrelation function, the packet detecting circuit will calculate and remove the error of the delay correlation function and the autocorrelation function produced by a DC offset. Then the packet detecting circuit calculates a packet triggering value according to the delay correlation function and the autocorrelation function for detecting the packet inputting time more precisely.

Abstract: A frequency synthesizer applied to a frequency hopping system includes a voltage controlled oscillator (VCO), a phase lock loop (PLL) system, a second frequency divider, a first SSB mixer, a second SSB mixer, and a multiplexer. The VCO generates an oscillating frequency. The PLL system includes a first frequency divider and divides the oscillating frequency by 10 to generate a first dividing signal. The second frequency divider divides the oscillating frequency by 2 to generate a second dividing signal and further divides the second dividing signal by 2 to generate a third dividing signal. The first SSB mixer mixes frequencies of the second and third dividing signals to generate a first mixing signal. The second SSB mixer mixes frequencies of the first mixing signal and the first dividing signal to generate a second mixing signal. The Multiplexer determines to output the first mixing signal or the second mixing signal.

Abstract: The present invention provides a circuit for canceling DC offset, comprising: a first circuit accumulating a first square value of a plurality of signal values in a time period; a second circuit calculation a second square value of an accumulation of said signal values in said time period, wherein said square value is divided by a quantity of said signal values in said time period to generate a DC offset value; and a third circuit, connected to said first circuit and second circuit, calculating a difference between said first square value and said DC offset value.

Abstract: A method accessing a flash memory storage device through universal serial bus (USB) of the present invention includes a flash controller and a flash memory, wherein the method includes connecting the storage device to a USB interface of an electronic device; outputting a plurality of accessing instructions to the flash controller via the electronic device; deciding which data is needed to be temporarily saved in a cache memory and a priority of the accessing instructions according to the characteristic of the file system and the content of preceding instructions of the flash controller; and writing the data temporarily saved in the cache memory into the flash memory according to the priority of the flash controller. The objective of the method of the present invention is to enhance the operation efficiency of the storage device.

Abstract: A USB peripheral device with dynamic modification class is connected to a basic system of processor through a USB transmission interface. The USB peripheral device contains a card connection unit and a USB microprocessor. By judging whether the card connection unit is inserted with a card device, the USB microprocessor is determined to transmit the data or not with the basic system of processor. If one card device is inserted into the card connection unit, the USB microprocessor outputs the corresponding class code according to the device class of the card device for the basic system of processor distinguishing and confirming said class code. Therefore, dynamically changing the device class in accordance with various card devices is achieved.

Abstract: A portable data storage device includes a control unit coupled via a predetermined interface with a computer having an operating system with user authority limits, and a memory divided into a segment I for storing related applications, a public segment II for temporarily storing instructions and data, and a hidden segment III for saving client data. In a method of accessing data via the portable data storage device, when the computer is to write data into or read data from the segment III, the data to be written or read is first temporarily stored in the segment II, and specific read or write instructions for a read/write level application interface are written into the segment II by the applications in the segment I and executed, so as to complete data exchange and access between the portable data storage device and the computer.

Abstract: A method of executing a default instruction set of a storage device for conveniently connecting the storage device to a computer includes the following steps: connecting a USB interface of the storage device to a USB interface of the computer; the computer using interface commands to determine a device class of the storage device; a controller of the storage device actuating a built-in Auto Dispatch program and returning a message to the computer that the connected device is a keyboard; the controller sending specific serial keyboard commands to the computer via the Auto Dispatch program; the controller resetting an interface class code setting thereof when the computer has received the specific serial keyboard commands; the computer using the interface commands to check the interface class code setting to identify the storage device; and the controller returning a message to the computer that the connected device is a mass storage device.

Abstract: A USB peripheral device with dynamic modification class is connected to a basic system of processor through a USB transmission interface. The USB peripheral device contains a card connection unit and a USB microprocessor. By judging whether the card connection unit is inserted with a card device, the USB microprocessor is determined to transmit the data or not with the basic system of processor. If one card device is inserted into the card connection unit, the USB microprocessor outputs the corresponding class code according to the device class of the card device for the basic system of processor distinguishing and confirming said class code. Therefore, dynamically changing the device class in accordance with various card devices is achieved.

Abstract: A silicon storage apparatus is adapted to a processor base system and comprises a plurality of storage media interfaces and a controller. The storage media interfaces are separately used to contain and connect a storage medium and the controller is electrically connected with the storage media interfaces for providing a data transmission channel to the storage media according to a detecting signal, and outputting an indicating message to the processor base system when another detecting signal produced. Whereby, the sizes of the silicon storage apparatus and the controller can be reduced substantially.

Abstract: An integrated hub control chip is applied to a motherboard of an application system. The integrated hub control chip contains an upstream port transceiver, an upstream port controller, a relaying circuit unit, a keyboard control module, a digital camera control module, a storage medium control module, and a relaying circuit controller. The keyboard control module, the digital camera control module, and the storage medium control module are directly connected to the relaying circuit controller. The relaying circuit controller switches the transmission path of the relaying circuit unit according to the transmission speed of these control modules. The upstream port controller controls the transmission direction of the upstream port transceiver to accomplish the data communication with the motherboard. The objects of saving the circuit space of motherboard, reducing the hardware cost, and increasing the purposes and expansibility of the integrated hub control chip can therefore be achieved.

Abstract: A method for I/Q adjustment is disclosed. The method includes delaying phases of an in-phase signal and a quadrature signal with a predetermined angle for generating an in-phase delay signal and a quadrature delay signal; adjusting magnitudes of the in-phase signal, the quadrature signal, the in-phase delay signal, and the quadrature delay signal according to a magnitude difference signal and a phase control signal; adding the adjusted in-phase signal and the adjusted in-phase delay signal; and adding the adjusted quadrature signal and the adjusted quadrature delay signal.

Abstract: The present invention discloses an improved card reader assembly, and more particularly an improved adapter assembly of a card reader that stacks the components in the space as to achieve the effect of saving the area and volume of the adapter of the card reader. The improved card reader assembly is an improved adapter assembly that includes a card base, and the card base includes a circuit board and at least one slot. The circuit board has a plurality of lead terminals electrically coupled to a memory card that is inserted into the slot; a top cover; and a chip and an oscillating crystal are installed in the adapter body at a position between the top cover and the card base. The chip is situated between the lead terminal of the card base and the slot, and the chip and the oscillating crystal are electrically connected to the circuit board, and a terminal set is installed onto the adapter body and electrically connected to the circuit board and the chip.