Abstract: A semiconductor device includes a substrate, a first magnetic tunnel junction (MTJ) structure, a second MTJ structure, and an interconnection structure. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction, and the interconnection structure includes a first metal interconnection and a second metal interconnection. The second metal interconnection is disposed on and contacts the first metal interconnection.

Abstract: Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.

Abstract: A power supply with duty cycle limiting circuit includes a conversion circuit, a drive circuit, a control unit, and a duty cycle limiting circuit. The duty cycle limiting circuit converts a control signal into a control voltage, and determines whether a power switch of a power supply is turned off according to the control voltage and a threshold voltage to limit a duty cycle of the power switch.

Abstract: A semiconductor device includes a substrate comprising a MTJ region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a contact plug on the logic region. Preferably, the MTJ includes a bottom electrode layer having a gradient concentration, a free layer on the bottom electrode layer, and a top electrode layer on the free layer.

Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.

Abstract: A device for achieving dynamic charging and balance of battery cells is disclosed. The device is configured for monitoring a plurality of battery voltages from a plurality of battery cells in a multi-cell battery pack. In case of a battery voltage difference between two of the battery cells being greater than a pre-determined voltage difference, the device generates a plurality of balance charging currents for charging the battery cells. In which, each of the balance charging currents is calculated based on remaining charge time, measured battery voltage, and rated battery capacity. Thus, in a charge cycle, one balance charging current for charging the battery cell with low battery voltage is designed to be greater than another one balance charging current for charging the battery cell with high battery voltage. Consequently, elimination of the battery voltage difference existing between any two of the battery cells is achieved.

Abstract: A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.

Abstract: A floor types identifying device for use in a vacuum cleaner is disclosed, and comprises a current sensing unit coupled and a processing and controlling module. When a suction head is moved, a driving current of a roller brush driving motor is detected by the current sensing unit, such that the processing and controlling module judges that the suction head is moved on a specific floor that has a hard surface, a short-pile-carpeted surface or a long-pile-carpeted surface according to a variation of the driving current. Therefore, for a vacuum cleaner that is integrated with the floor types identifying device of the present invention, both suction power of the vacuum cleaner and driving power of the roller driving motor can be properly adjusted in response to the floor's surficial material type.

Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a bottom electrode layer on the IMD layer, wherein the bottom electrode layer comprises a gradient concentration; forming a free layer on the bottom electrode layer; forming a top electrode layer on the free layer; and patterning the top electrode layer, the free layer, and the bottom electrode layer to form a magnetic tunneling junction (MTJ).

Abstract: A data transmission method, applied to a data transmission device connected to a first host and a second host, comprising: (a) activating a console of the first host via a trigger operation and acquiring a source path of target data in the first host; (b) acquiring the target data from the source path and copying the target data to a storage circuit inside or outside the data transmission device; and (c) copying the target data from the storage circuit to the second host.

Abstract: A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.

Abstract: A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.

Abstract: A method for forming a semiconductor structure includes the steps of providing a substrate having a device region and an alignment mark region, forming a first dielectric layer on the substrate and a second dielectric layer on the first dielectric layer, forming a conductive via in the second dielectric layer on the device region, forming a mask layer on the second dielectric layer, etching the second dielectric layer and the first dielectric layer through an opening of the mask layer on the alignment mark region to form a first trench through the second dielectric layer and an upper portion of the first dielectric layer and a plurality of second trenches in the first dielectric layer directly under the first trench. Afterward, a memory stack structure is formed on the second dielectric layer, covering the conductive via and filling into the first trench and the second trenches.

Abstract: The disclosure provides a semiconductor memory device including a substrate having a memory cell region and an alignment mark region; a dielectric layer covering the memory cell region and the alignment mark region; conductive vias in the dielectric layer within the memory cell region; an alignment mark trench in the dielectric layer within the alignment mark region; and storage structures disposed on the conductive vias, respectively. Each of the storage structures includes a bottom electrode defined from a bottom electrode metal layer, a magnetic tunnel junction (MTJ) structure defined from an MTJ layer, and a top electrode. A residual metal stack is left in the alignment mark trench. The residual metal stack includes a portion of the bottom electrode metal layer and a portion of the MTJ layer.

Abstract: A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench.

Abstract: A signal transmission apparatus comprises a base and a shell, wherein a top portion of the base has a signal transmission device. The shell is covered above the base. A cavity is formed inside the shell. The cavity is in communication with an opening of a bottom portion of the shell. And the shell comprises a ceramic shell body and an inner covering layer. The inner covering layer is fully attached to an inner surface of the ceramic shell body. Therefore, the signals of the signal transmission device can pass through the shell so that the signal transmission device can receive or transmit signals. And through the strong adhesion of the inner covering layer, the ceramic shell body can be kept intact without being broken into a lot of debris when the ceramic shell body is impacted by external force or suddenly dropped.

Abstract: A signal transmission apparatus comprises a base and a shell, wherein a top portion of the base has a signal transmission device. The shell is covered above the base. A cavity is formed inside the shell. The cavity is in communication with an opening of a bottom portion of the shell. And the shell comprises a ceramic shell body and an inner covering layer. The inner covering layer is fully attached to an inner surface of the ceramic shell body. Therefore, the signals of the signal transmission device can pass through the shell so that the signal transmission device can receive or transmit signals. And through the strong adhesion of the inner covering layer, the ceramic shell body can be kept intact without being broken into a lot of debris when the ceramic shell body is impacted by external force or suddenly dropped.

Abstract: An intelligent fan control system with interface compatibility is provided. The intelligent fan control system can identify and control fans one-to-one connected to fan slots, and each fan slot includes four pins. The intelligent fan control system includes a bus; an I2C signal switching unit including SDA outputs one-to-one connected to third pin of the fan slots via the bus; an I2C signal switching unit including SCL outputs one-to-one connected to fourth pins of the fan slots via the bus; voltage control units one-to-one corresponding to the fan slots, and having output terminals one-to-one connected to second pins of the fan slots; connection line sets, and each connection line set including four connection lines and connected to the corresponding fan slot; a control board comprising port sets, and can control and switch the I2C signal switching unit to the fan slots in sequence, to transmit the corresponding I2C signal.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a cap layer on the first MTJ and the second MTJ; forming a passivation layer on the cap layer; removing part of the passivation layer to form a recess between the first MTJ and the second MTJ; forming an anti-reflective layer on the passivation layer and filling the recess; and removing the anti-reflective layer, the passivation layer, and the cap layer to form a first contact hole.

Abstract: An intelligent fan with interface compatibility is provided. The intelligent fan includes a fan body having a fan and a motor, a driving circuit, a tachometer, an output connector including a first pin, a second pin, a third pin and a fourth pin connected to a fan connector of a motherboard, and a microcontroller connected to the driving circuit and the tachometer, and connected to the motherboard via the first, second, third and fourth pins. When the intelligent fan is powered on, the microcontroller sets the third and fourth pins as input pins for receiving an output signal of the fan connector of the motherboard, and the microcontroller performs an I2C signal analysis on the output signal. When the I2C signal analysis succeeds, the intelligent fan is set in an I2C mode, and when the I2C signal analysis fails, the intelligent fan is set in a PWM mode.