Abstract: A DC uninterruptible power supply apparatus with bidirectional protection function receives a DC power source and supplies power to a DC load. The DC uninterruptible power supply apparatus includes a first loop, a second loop, a third loop, and a control unit. The first loop receives the DC power source and supplies power to the DC load. The second loop converts the DC power source into an energy-storing power source to charge an energy-storing unit. The energy-storing unit provides a backup power source to the DC load through the third loop and the first loop. The control unit controls the first loop, the second loop, and the third loop to correspondingly provide a first protection mechanism, a second protection mechanism, and a third protection mechanism.

Abstract: A power supply with duty cycle limiting circuit includes a conversion circuit, a drive circuit, a control unit, and a duty cycle limiting circuit. The duty cycle limiting circuit converts a control signal into a control voltage, and determines whether a power switch of a power supply is turned off according to the control voltage and a threshold voltage to limit a duty cycle of the power switch.

Abstract: A DC uninterruptible power supply apparatus with bidirectional protection function receives a DC power source and supplies power to a DC load. The DC uninterruptible power supply apparatus includes a first loop, a second loop, a third loop, and a control unit. The first loop receives the DC power source and supplies power to the DC load. The second loop converts the DC power source into an energy-storing power source to charge an energy-storing unit. The energy-storing unit provides a backup power source to the DC load through the third loop and the first loop. The control unit controls the first loop, the second loop, and the third loop to correspondingly provide a first protection mechanism, a second protection mechanism, and a third protection mechanism.

Abstract: A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench.

Abstract: Disclosures of the present invention describe a switch device has a controlling and processing unit comprising a first zero point detector, a second zero point detector, an arc detector, and a microcontroller. According to zero crossing point of input voltage signal, zero crossing point of output voltage signal, relay's delay time, and arc-spark-induced signal, the microcontroller is capable of adaptively generating a relay controlling signal to control the relay, such that the relay achieves a short-circuit switching at the zero cross point of output voltage signal for making the output voltage signal be transmitted to at least one load device. Moreover, the microcontroller is also able to control the relay to finish a short-circuit switching at the zero cross point of input voltage signal, so as to stop the output voltage signal from being transmitted to the load device.

Abstract: A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a cap layer on the first MTJ and the second MTJ; forming a passivation layer on the cap layer; removing part of the passivation layer to form a recess between the first MTJ and the second MTJ; forming an anti-reflective layer on the passivation layer and filling the recess; and removing the anti-reflective layer, the passivation layer, and the cap layer to form a first contact hole.

Abstract: The disclosure provides a semiconductor memory device including a substrate having a memory cell region and an alignment mark region; a dielectric layer covering the memory cell region and the alignment mark region; conductive vias in the dielectric layer within the memory cell region; an alignment mark trench in the dielectric layer within the alignment mark region; and storage structures disposed on the conductive vias, respectively. Each of the storage structures includes a bottom electrode defined from a bottom electrode metal layer, a magnetic tunnel junction (MTJ) structure defined from an MTJ layer, and a top electrode. A residual metal stack is left in the alignment mark trench. The residual metal stack includes a portion of the bottom electrode metal layer and a portion of the MTJ layer.

Abstract: Disclosures of the present invention describe a current sensing device and method, wherein the current sensing device comprises: at least one magnetic sensor, a signal receiving unit and a microprocessor. Particularly, the present invention provides an environmental magnetic field filtering unit and an effective current calculation unit in the microprocessor, such that the microprocessor is able to calculate the value of a current flowing in a specific electrical cable with high accuracy based on a sensing magnetic field outputted from the magnetic sensor.

Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a bottom electrode layer on the IMD layer, wherein the bottom electrode layer comprises a gradient concentration; forming a free layer on the bottom electrode layer; forming a top electrode layer on the free layer; and patterning the top electrode layer, the free layer, and the bottom electrode layer to form a magnetic tunneling junction (MTJ).

Abstract: A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench.

Abstract: A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.

Abstract: The disclosure provides a semiconductor memory device including a substrate having a memory cell region and an alignment mark region; a dielectric layer covering the memory cell region and the alignment mark region; conductive vias in the dielectric layer within the memory cell region; an alignment mark trench in the dielectric layer within the alignment mark region; and storage structures disposed on the conductive vias, respectively. Each of the storage structures includes a bottom electrode defined from a bottom electrode metal layer, a magnetic tunnel junction (MTJ) structure defined from an MTJ layer, and a top electrode. A residual metal stack is left in the alignment mark trench. The residual metal stack includes a portion of the bottom electrode metal layer and a portion of the MTJ layer.

Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a bottom electrode layer on the IMD layer, wherein the bottom electrode layer comprises a gradient concentration; forming a free layer on the bottom electrode layer; forming a top electrode layer on the free layer; and patterning the top electrode layer, the free layer, and the bottom electrode layer to form a magnetic tunneling junction (MTJ).

Abstract: An intelligent fan control system with interface compatibility is provided. The intelligent fan control system can identify and control fans one-to-one connected to fan slots, and each fan slot includes four pins. The intelligent fan control system includes a bus; an I2C signal switching unit including SDA outputs one-to-one connected to third pin of the fan slots via the bus; an I2C signal switching unit including SCL outputs one-to-one connected to fourth pins of the fan slots via the bus; voltage control units one-to-one corresponding to the fan slots, and having output terminals one-to-one connected to second pins of the fan slots; connection line sets, and each connection line set including four connection lines and connected to the corresponding fan slot; a control board comprising port sets, and can control and switch the I2C signal switching unit to the fan slots in sequence, to transmit the corresponding I2C signal.

Abstract: An intelligent fan with interface compatibility is provided. The intelligent fan includes a fan body having a fan and a motor, a driving circuit, a tachometer, an output connector including a first pin, a second pin, a third pin and a fourth pin connected to a fan connector of a motherboard, and a microcontroller connected to the driving circuit and the tachometer, and connected to the motherboard via the first, second, third and fourth pins. When the intelligent fan is powered on, the microcontroller sets the third and fourth pins as input pins for receiving an output signal of the fan connector of the motherboard, and the microcontroller performs an I2C signal analysis on the output signal. When the I2C signal analysis succeeds, the intelligent fan is set in an I2C mode, and when the I2C signal analysis fails, the intelligent fan is set in a PWM mode.

Abstract: The invention discloses a power saving device capable of automatically sensing standby current, which is used in a power device such as a power outlet or other power supply devices for giving the power device ability of electricity saving. When the power saving device normally works, a threshold current setting unit of a controlling and processing module is configured to automatically calculate a threshold current based on current signals sensed by a current detecting unit under different operation modes of at least one electrical device electrically connected to the power device. Moreover, when at least one standby current sensed from the electrical device is determined to be lower than the threshold current, the controlling and processing module immediately switches a switch unit to an open-circuit state, thereby causing the electrical device unable to receive electricity from the power device. Consequently, the power device exhibits the ability of power saving.

Abstract: A device for real-time self-diagnosis of a fan and a method are disclosed for detecting whether a fan body encounters an environment abnormal situation. The fan body includes a motor, a fan and a tachometer. The fan body further includes a microcontroller for receiving a speed signal of the tachometer and calculating a speed value of the fan, and detecting a current value of the motor during operation. The microcontroller can control the motor to drive the fan according to a monitoring period and a control signal transmitted from the control board, and can calculate a speed change amount according to the monitoring period, and can calculate a current change amount. When the speed change amount exceeds a speed change threshold and the current change amount exceeds a current change threshold for a period of time, the microcontroller generates an environmental anomaly signal.

Abstract: Disclosures of the present invention describe a switch device has a controlling and processing unit comprising a first zero point detector, a second zero point detector, an arc detector, and a microcontroller. According to zero crossing point of input voltage signal, zero crossing point of output voltage signal, relay's delay time, and arc-spark-induced signal, the microcontroller is capable of adaptively generating a relay controlling signal to control the relay, such that the relay achieves a short-circuit switching at the zero cross point of output voltage signal for making the output voltage signal be transmitted to at least one load device. Moreover, the microcontroller is also able to control the relay to finish a short-circuit switching at the zero cross point of input voltage signal, so as to stop the output voltage signal from being transmitted to the load device.

Abstract: The disclosure provides a semiconductor memory device including a substrate having a memory cell region and an alignment mark region; a dielectric layer covering the memory cell region and the alignment mark region; conductive vias in the dielectric layer within the memory cell region; an alignment mark trench in the dielectric layer within the alignment mark region; and storage structures disposed on the conductive vias, respectively. Each of the storage structures includes a bottom electrode defined from a bottom electrode metal layer, a magnetic tunnel junction (MTJ) structure defined from an MTJ layer, and a top electrode. A residual metal stack is left in the alignment mark trench. The residual metal stack includes a portion of the bottom electrode metal layer and a portion of the MTJ layer.