Patents by Inventor Chia Chang

Chia Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240123463
    Abstract: An atomization module includes a main fixing member, an auxiliary fixing member, an atomization component and a piezoelectric component. The main fixing member includes a first bonding part, a second bonding part and a connecting part. The first bonding part has a first opening and a first bonding surface surrounding the first opening. The second bonding part is connected to the first bonding part, and the connecting part and the second bonding part surround the first bonding part. The auxiliary fixing member has a second opening and a second bonding surface surrounding the second opening. The piezoelectric component surrounds the first bonding part. The main fixing member has a first adhesive groove, which is jointly defined at least by the main fixing member, the auxiliary fixing member and the atomization component. The first adhesive is provided in the first adhesive groove.
    Type: Application
    Filed: October 2, 2023
    Publication date: April 18, 2024
    Inventors: CHANG-HSIEH YAO, HSUN-WEI CHIANG, CHIA-CHIEN CHANG, HSIN-YI PAI, CHUN-CHIA JUAN
  • Publication number: 20240128876
    Abstract: A switching control circuit for use in controlling a resonant flyback power converter generates a first driving signal and a second driving signal. The first driving signal is configured to turn on the first transistor to generate a first current to magnetize a transformer and charge a resonant capacitor. The transformer and charge a resonant capacitor are connected in series. The second driving signal is configured to turn on the second transistor to generate a second current to discharge the resonant capacitor. During a power-on period of the resonant flyback power converter, the second driving signal includes a plurality of short-pulses configured to turn on the second transistor for discharging the resonant capacitor. A pulse-width of the short-pulses of the second driving signal is short to an extent that the second current does not exceed a current limit threshold.
    Type: Application
    Filed: June 15, 2023
    Publication date: April 18, 2024
    Inventors: Yu-Chang Chen, Ta-Yung Yang, Kun-Yu Lin, Fu-Ciao Syu, Chia-Hsien Yang, Hsin-Yi Wu
  • Patent number: 11960253
    Abstract: A system and a method for parameter optimization with adaptive search space and a user interface using the same are provided. The system includes a data acquisition unit, an adaptive adjustment unit and an optimization search unit. The data acquisition unit obtains a set of executed values of several operating parameters and a target parameter. The adaptive adjustment unit includes a parameter space transformer and a search range definer. The parameter space transformer performs a space transformation on a parameter space of the operating parameters according to the executed values. The search range definer defines a parameter search range in a transformed parameter space based on the sets of the executed values. The optimization search unit takes the parameter search range as a limiting condition and takes optimizing the target parameter as a target to search for a set of recommended values of the operating parameters.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: April 16, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Po-Yu Huang, Chun-Fang Chen, Hong-Chi Ku, Te-Ming Chen, Chien-Liang Lai, Sen-Chia Chang
  • Patent number: 11961919
    Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chung Chang, Hsiu-Hao Tsao, Ming-Jhe Sie, Shun-Hui Yang, Chen-Huang Huang, An Chyi Wei, Ryan Chia-Jen Chen
  • Publication number: 20240120844
    Abstract: A resonant flyback power converter includes: a first and a second transistors which form a half-bridge circuit for switching a transformer and a resonant capacitor to generate an output voltage; a current-sense device for sensing a switching current of the half-bridge circuit to generate a current-sense signal; and a switching control circuit generating a first and a second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal controls the half-bridge circuit to generate a positive current to magnetize the transformer and charge the resonant capacitor. The turn-on of the second driving signal controls the half-bridge circuit to generate a negative current to discharge the resonant capacitor. The switching control circuit turns off the first transistor when the positive current exceeds a positive-over-current threshold, and/or, turns off the second transistor when the negative current exceeds a negative-over-current threshold.
    Type: Application
    Filed: April 10, 2023
    Publication date: April 11, 2024
    Inventors: Kun-Yu LIN, Ta-Yung YANG, Yu-Chang CHEN, Hsin-Yi WU, Fu-Ciao SYU, Chia-Hsien YANG
  • Publication number: 20240122078
    Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 11, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Chang Hsu, Tang-Chun Weng, Cheng-Yi Lin, Yung-Shen Chen, Chia-Hung Lin
  • Patent number: 11950902
    Abstract: The present invention provides a micro biosensor for reducing a measurement interference when measuring a target analyte in the biofluid, including: a substrate; a first working electrode configured on the surface, and including a first sensing section; a second working electrode configured on the surface, and including a second sensing section which is configured adjacent to at least one side of the first sensing section; and a chemical reagent covered on at least a portion of the first sensing section for reacting with the target analyte to produce a resultant. When the first working electrode is driven by a first working voltage, the first sensing section measures a physiological signal with respect to the target analyte. When the second working electrode is driven by a second working voltage, the second conductive material can directly consume the interferant so as to continuously reduce the measurement inference of the physiological signal.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: April 9, 2024
    Assignee: Bionime Corporation
    Inventors: Chun-Mu Huang, Chieh-Hsing Chen, Heng-Chia Chang, Chi-Hao Chen, Pi-Hsuan Chen
  • Patent number: 11956994
    Abstract: The present disclosure is generally related to 3D imaging capable OLED displays. A light field display comprises an array of 3D light field pixels, each of which comprises an array of corrugated OLED pixels, a metasurface layer disposed adjacent to the array of 3D light field pixels, and a plurality of median layers disposed between the metasurface layer and the corrugated OLED pixels. Each of the corrugated OLED pixels comprises primary or non-primary color subpixels, and produces a different view of an image through the median layers to the metasurface to form a 3D image. The corrugated OLED pixels combined with a cavity effect reduce a divergence of emitted light to enable effective beam direction manipulation by the metasurface. The metasurface having a higher refractive index and a smaller filling factor enables the deflection and direction of the emitted light from the corrugated OLED pixels to be well controlled.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: April 9, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Chung-Chih Wu, Hoang Yan Lin, Guo-Dong Su, Zih-Rou Cyue, Li-Yu Yu, Wei-Kai Lee, Guan-Yu Chen, Chung-Chia Chen, Wan-Yu Lin, Gang Yu, Byung-Sung Kwak, Robert Jan Visser, Chi-Jui Chang
  • Patent number: 11953614
    Abstract: A method for measuring coordinate position include detecting the distance of a target relative to a portable electronic device to generate a measurement signal corresponding to the distance, sensing a relative position of the target to generate a azimuth angle corresponding to the relative position, detecting the movement of the portable electronic device to generate an inertial signal corresponding to the movement, obtaining positioning information of the portable electronic device, converting the measurement signal into distance data, converting the inertial signal into a tilt angle, calculating coordinate difference information with the tilt angle, the distance data and the azimuth angle, and calculating coordinate position of the target with the positioning information and the coordinate difference information.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: April 9, 2024
    Assignee: Getac Technology Corporation
    Inventors: Chia-Chang Chiu, Wei-Rong Chen
  • Publication number: 20240113071
    Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.
    Type: Application
    Filed: January 5, 2023
    Publication date: April 4, 2024
    Inventors: Chung-Shi Liu, Mao-Yen Chang, Yu-Chia Lai, Kuo-Lung Pan, Hao-Yi Tsai, Ching-Hua Hsieh, Hsiu-Jen Lin, Po-Yuan Teng, Cheng-Chieh Wu, Jen-Chun Liao
  • Publication number: 20240113154
    Abstract: A semiconductor device may include a compound substrate and a 3-dimensional inductor structure. The compound substrate may include a front surface and a back surface. The 3-dimensional inductor structure may include a front conductive stack, a back conductive layer, and at least one through-hole structure. At least one portion of the front conductive stack may include a first conductive layer disposed on the front surface of the compound substrate, and a second conductive layer disposed on the first conductive layer. The second conductive layer has a thickness ranging between 30 micrometers and 400 micrometers. The back conductive layer is disposed on the back surface of the compound substrate. The at least one through-hole structure penetrates through the compound substrate, and electrically connects the front conductive stack to the back conductive layer.
    Type: Application
    Filed: November 20, 2022
    Publication date: April 4, 2024
    Applicant: RichWave Technology Corp.
    Inventors: Chia-Wei Chang, Yan-Han Huang, Chin-Chia Chang
  • Publication number: 20240111118
    Abstract: A lens shift backlash elimination device includes a base, a transmission mechanism, and a lens. The transmission mechanism is disposed on the base and includes a first element, a second element, and an elastic element. The second element is mechanically connected to the first element. The elastic element is disposed between the first element and the second element, or abutted against the first element. The lens is mechanically connected to the transmission mechanism. The lens may be displaced relative to the base in a first direction.
    Type: Application
    Filed: November 3, 2022
    Publication date: April 4, 2024
    Applicant: Young Optics Inc.
    Inventors: Chia-Chang Lee, Chi-Yu Meng
  • Publication number: 20240113113
    Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Chih-Chang Hung, Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Yi-Hsuan Hsiao, I-Wei Yang
  • Publication number: 20240113112
    Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
  • Publication number: 20240112969
    Abstract: An in-mold electronic (IME) device includes a curved substrate, a first conductive layer, a dielectric layer, a gap compensation layer, and a second conductive layer. The curved substrate has a first surface. The first conductive layer is disposed on the first surface. The dielectric layer is disposed on the first conductive layer and has a first thickness. The gap compensation layer is disposed on the first surface and connected to the dielectric layer. The gap compensation layer has a second thickness. The second conductive layer is disposed on the gap compensation layer and electrically connected to the gap compensation layer. A curvature radius of the curved substrate is c, a ratio of the second thickness to the first thickness is r, and c and r satisfy a relationship: r=1.5?0.02c±15%.
    Type: Application
    Filed: July 28, 2023
    Publication date: April 4, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Ming Peng, Hsiao-Fen Wei, Chih-Chia Chang
  • Patent number: 11949376
    Abstract: A VCO (voltage-controlled oscillator) includes: a resonant tank having a parallel connection of an inductor, a fixed capacitor, a variable capacitor, a first temperature compensating capacitor, and a second temperature compensating capacitor across a first node and a second node, and configured to establish an oscillation of a first oscillatory voltage at the first node and a second oscillatory voltage at the second node; and a regenerative network placed across the first node and the second node to provide energy to sustain the oscillation. The variable capacitor is controlled by a control voltage, the first temperature compensating capacitor is controlled by a first temperature tracking voltage of a positive temperature coefficient, and the second temperature compensating capacitor is controlled by a second temperature tracking voltage of a negative temperature coefficient.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: April 2, 2024
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: I-Chang Wu, Chia-Liang (Leon) Lin
  • Patent number: 11948935
    Abstract: Provided is a tap cell including a substrate, a first well, a second well, a first doped region, and the second doped region. The substrate has a first region and a second region. The first well has a first dopant type and includes a first portion disposed in the first region and a second portion extending into the second region. The second well has a second dopant type and includes a third portion disposed in the second region and a fourth portion extending into the first region. The first doped region having the first dopant type is disposed in the second portion of the first well and the third portion of the second well along the second region. The second doped region having the second dopant type is disposed in the first portion of the first well and the fourth portion of the second well along the first region.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Feng Chang, Bao-Ru Young, Tung-Heng Hsieh, Chun-Chia Hsu
  • Publication number: 20240103377
    Abstract: A composition and method for removing a metal-containing layer or portion of a layer of a pellicle of an EUV mask are provided. The composition includes water; one or more oxidizing agents; and one or more acids. The method includes forming one or more layers over a silicon substrate with at least one of those layers includes a metal containing layer and removing the metal containing layer by contacting the metal containing layer with the composition of the disclosed and claimed subject matter.
    Type: Application
    Filed: October 15, 2020
    Publication date: March 28, 2024
    Applicant: Versum Materials US, LLC
    Inventors: CHAO-HSIANG CHEN, CHUNG-YI CHANG, YI-CHIA LEE, WEN DAR LIU
  • Publication number: 20240107414
    Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for switching a secondary cell to a primary cell. A user equipment (UE) monitors a first radio condition of the UE for beams of a primary cell and a second radio condition for beams of one or more secondary cells configured for the UE in carrier aggregation. The UE transmits a request to configure a candidate beam of at least one candidate secondary cell as a new primary cell in response to the first radio condition not satisfying a first threshold and the second radio condition for the at least one candidate secondary cell satisfying a second threshold. A base station determines to reconfigure at least one secondary cell as the new primary cell. The base station and the UE perform a handover of the UE to the new primary cell.
    Type: Application
    Filed: September 23, 2022
    Publication date: March 28, 2024
    Inventors: Yu-Chieh HUANG, Kuhn-Chang LIN, Jen-Chun CHANG, Wen-Hsin HSIA, Chia-Jou LU, Sheng-Chih WANG, Chenghsin LIN, Yeong Leong CHOO, Chun-Hsiang CHIU, Chihhung HSIEH, Kai-Chun CHENG, Chung Wei LIN
  • Patent number: 11939432
    Abstract: Synthetic amino acid-modified polymers and methods of making the same and using the same are disclosed. The synthetic amino acid-modified polymers possess distinct thermosensitive, improved water-erosion resistant, and enhanced mechanical properties, and are suitable of reducing or preventing formation of postoperative tissue adhesions. Additionally, the amino acid-modified polymers can also be used as a vector to deliver pharmaceutically active agents.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: March 26, 2024
    Assignee: PROVIEW-MBD BIOTECH CO., LTD.
    Inventors: Yu-Chia Chang, Yunn-Kuen Chang, Wen-Yen Huang, Ging-Ho Hsiue, Hsieh-Chih Tsai, Shuian-Yin Lin, Nai-Sheng Hsu, Tzu-Yu Lin