Patents by Inventor Chia Chang

Chia Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11915980
    Abstract: Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ya-Yi Tsai, Yi-Hsuan Hsiao, Shu-Yuan Ku, Ryan Chia-Jen Chen, Ming-Ching Chang
  • Publication number: 20240049608
    Abstract: A semiconductor device includes a substrate, a first MTJ structure, a second MTJ structure, an interconnection structure including a first metal interconnection and a second metal interconnection disposed on and contacting the first metal interconnection, a fifth metal interconnection, and a sixth metal interconnection. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction. The fifth metal interconnection and the sixth metal interconnection are disposed under and contact the first MTJ structure and the second MTJ structure, respectively. The fifth metal interconnection includes a barrier layer and a metal layer disposed on the barrier layer. A length of the first MTJ structure in the first horizontal direction is greater than a length of the metal layer in the first horizontal direction.
    Type: Application
    Filed: October 18, 2023
    Publication date: February 8, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Chia-Chang Hsu
  • Patent number: 11895927
    Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: February 6, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Chang Hsu, Tang-Chun Weng, Cheng-Yi Lin, Yung-Shen Chen, Chia-Hung Lin
  • Patent number: 11892704
    Abstract: A lens device including a lens barrel, a lens, a linear reciprocating motion mechanism, and a power machine is provided. The lens is disposed in the lens barrel. The linear reciprocating motion mechanism includes a first movable part and a second movable part. The first movable part is coupled to the lens barrel. The second movable part is coupled to the first movable part. The power machine is coupled to the second movable part to drive the second movable part to rotate, thereby driving the first movable part, and the first movable part drives the lens barrel to perform a linear reciprocating motion, wherein when the second movable part is rotated by N turns, the first movable part is rotated by one turn, and N is greater than or equal to 10.
    Type: Grant
    Filed: November 26, 2020
    Date of Patent: February 6, 2024
    Assignee: Young Optics Inc.
    Inventors: Yi-Feng Yen, Chia-Chang Lee
  • Patent number: 11882986
    Abstract: A floor types identifying device for use in a vacuum cleaner is disclosed, and comprises a current sensing unit coupled and a processing and controlling module. When a suction head is moved, a driving current of a roller brush driving motor is detected by the current sensing unit, such that the processing and controlling module judges that the suction head is moved on a specific floor that has a hard surface, a short-pile-carpeted surface or a long-pile-carpeted surface according to a variation of the driving current. Therefore, for a vacuum cleaner that is integrated with the floor types identifying device of the present invention, both suction power of the vacuum cleaner and driving power of the roller driving motor can be properly adjusted in response to the floor's surficial material type.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: January 30, 2024
    Assignee: TALENTONE HONG KONG LIMITED
    Inventors: Chia-Chang Hsu, Fu-Yuen Fong, Kwok Lit Chan
  • Patent number: 11883418
    Abstract: A compound TSYI-ZAC (Zhankuic acid C) used in a method for treating dengue virus infection, in which a pharmaceutical composition can further comprise a 4,7-dimethoxy-5-methyl-1,3-benzodioxole compound capable of inhibiting dengue virus infection by down-regulating an expression of IL-6 and IL-8, and increasing a secretion of IFN-?.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: January 30, 2024
    Assignee: SYI BIOTECHNOLOGY CO., LTD.
    Inventors: Chia-Chang Chen, Guey-Chuen Perng, Hsiu-Man Lien, Yi-Ju Chen
  • Patent number: 11887529
    Abstract: A pixel array is provided. The pixel array includes a plurality of pixels, wherein each of the pixels includes a light emitting diode, a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor receives a first data signal and a first scan signal. The second transistor is coupled to the first transistor and an anode of the light emitting diode. The third transistor receives a system high voltage and a first control signal, and is coupled to the second transistor. The fourth transistor is coupled to an anode of a light emitting diode of an adjacent pixel, a control terminal of the third transistor, and a cathode of the light emitting diode. The fifth transistor is coupled to the cathode of the light emitting diode, and receives a second control signal and a system low voltage.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: January 30, 2024
    Assignee: Au Optronics Corporation
    Inventors: Ya-Jung Wang, Jing-Wun Jhang, Rong-Fu Lin, Nien-Chen Li, Hsien-Chun Wang, Che-Chia Chang, June Woo Lee, Hsin-Ying Lin, Chia-Ting Hsieh, Chien-Fu Huang, Sung-Yu Su
  • Publication number: 20240032440
    Abstract: A semiconductor device includes a substrate comprising a MTJ region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a contact plug on the logic region. Preferably, the MTJ includes a bottom electrode layer having a gradient concentration, a free layer on the bottom electrode layer, and a top electrode layer on the free layer.
    Type: Application
    Filed: October 3, 2023
    Publication date: January 25, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chia-Chang Hsu, Chen-Yi Weng, Chin-Yang Hsieh, Jing-Yin Jhang
  • Patent number: 11867758
    Abstract: Embodiments of the present disclosure provide a test method and apparatus for a control chip, and an electronic device, which relate to the field of semiconductor device test technologies. The control chip includes a built-in self-test BIST circuit. The method is performed by the BIST circuit. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: January 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Chuanqi Shi, Heng-Chia Chang, Li Ding, Jie Liu, Jun He, Zhan Ying
  • Publication number: 20240002781
    Abstract: Described herein is a method for encapsulating single cells using alternating current electrospray technology in tip streaming mode. The encapsulation efficiency is over 80% and natural (alginate, collagen) and synthetic (NorHA) hydrogels and various cell types can be used. The encapsulated cells can be implanted and are protected from the host's immune response. In addition, the coating allows better tissue growth in laboratory cell cultures with a conformal mechanical support that allows molecular and nutrient transport.
    Type: Application
    Filed: December 3, 2021
    Publication date: January 4, 2024
    Inventors: Hsueh-Chia Chang, Zehao Pan, Vivek Yadav, Loan Bui, Donny Hanjaya-Putra
  • Patent number: 11862268
    Abstract: Embodiments of the present disclosure provide a test method and apparatus for a control chip, an electronic device, relating to the field of semiconductor device test technology. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, a memory chip can be used for storing test vectors for a control chip, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Chuanqi Shi, Heng-Chia Chang, Li Ding, Jie Liu, Jun He, Zhan Ying
  • Publication number: 20230420035
    Abstract: An in-memory computing circuit includes an initial computing circuit and a target computing circuit. Herein, the initial computing circuit is configured to perform first operation processing on first data and second data to output a first operation result, and perform second operation processing on the first data and the second data to output a second operation result. The target computing circuit is configured to perform the first operation processing on the second operation result and the first operation result to output a first target result, and perform the second operation processing on the first data and the second operation result to output a second target result.
    Type: Application
    Filed: February 8, 2023
    Publication date: December 28, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: HENG-CHIA CHANG
  • Publication number: 20230419883
    Abstract: A display device includes a multiple of light-emitting elements and a multiple of driving circuits. Each of the multiple of driving circuits is configured to generate a driving current flowing through one of the multiple of light-emitting elements. Each of the multiple of driving circuits includes a first transistor, a second transistor, a reset circuit, a first control circuit and a second control circuit. The driving current flows from a first system high voltage terminal through the first transistor, the second transistor and one of the multiple of light-emitting elements to a system low voltage terminal. The first control circuit is configured to control the first transistor to modulate pulse amplitude of the driving current. The second control circuit is configured to control the second transistor to modulate pulse width of the driving current.
    Type: Application
    Filed: September 7, 2023
    Publication date: December 28, 2023
    Inventors: Che-Chia CHANG, Shang-Jie WU, Yu-Chieh KUO, Hsien-Chun WANG, Sin-An LIN, Mei-Yi LI, Yu-Hsun CHIU, Ming-Hung CHUANG, Yi-Jung CHEN
  • Patent number: 11851534
    Abstract: A method for preparing a fiber-containing molding compound includes the acts of a) providing a composite material which includes a first resin and fibers impregnated with the first resin, and b) mixing the composite material with a treatment medium which includes a diluent to form a mixture. The fiber-containing molding compound thus prepared has an adjustable fiber content.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: December 26, 2023
    Assignee: SRAM, LLC
    Inventors: Hung I Chen, Chia-Chang Chang, Ching-Han Liu, Huan-Ching Hsu
  • Patent number: 11854642
    Abstract: A memory test method includes: testing a first memory to acquire defect information of the first memory; acquiring repair information of the first memory according to the defect information of the first memory; and storing the repair information of the first memory in a second memory. In the technical solutions provided in the embodiments of the present disclosure, other memories may be used to store the repair information of the currently tested memory, so that the storage space can be increased and the test efficiency can be improved.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: December 26, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Heng-Chia Chang, Li Ding, Chuanqi Shi
  • Patent number: 11856870
    Abstract: A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: December 26, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Yi-Syun Chou, Ko-Wei Lin, Pei-Hsun Kao, Wei Chen, Chia-Fu Cheng, Chun-Yao Yang, Chia-Chang Hsu
  • Publication number: 20230404346
    Abstract: A device for conducting motor recognition and protection is disclosed. The device comprises a current detection circuit and a microprocessor, of which the current detection circuit is used for detecting an operation current from a roller brush driving motor that is integrated in a suction head of a vacuum cleaner. Moreover, the microprocessor is configured for determining a product model of the roller brush driving motor based on the operation current, deciding a protection parameter set according to the product model, and conducting a motor protection for the roller brush driving motor after loading at least one motor protection parameter contained by the protection parameter set.
    Type: Application
    Filed: May 24, 2023
    Publication date: December 21, 2023
    Applicant: PROLIFIC TECHNOLOGY INC.
    Inventors: CHIA-CHANG HSU, REN-YUAN YU
  • Publication number: 20230411972
    Abstract: A driving circuit applied to a protection switch of a battery module is disclosed. The driving circuit includes a reverse switch, a non-reverse switch, a capacitor, and a storing energy component. The reverse switch or the non-reverse switch is turned on or off by a PWM signal. When the PWM signal is at a high level, the reverse switch is turned off, the non-reverse switch is turned on, and the capacitor is charged via a battery total voltage to form a storage voltage on the capacitor. When the PWM signal is at a low level, the reverse switch is turned on, the non-reverse switch is turned off, a reference voltage is connected to the capacitor via the reverse switch to form a boosted voltage superimposed by the reference voltage and the storage voltage. Afterwards, the boosted voltage can be used to drive the protection switch to be turned on.
    Type: Application
    Filed: March 23, 2023
    Publication date: December 21, 2023
    Inventors: Wen-Fan Chang, Chun-Chieh Li, Chun-Wei Ma, Chia-Chang Chen
  • Publication number: 20230404031
    Abstract: A biometric monitoring device for an animal ear includes a male portion on a first side of the ear including a base having an upper surface towards the first side including openings and a protrusion having an upper portion for penetrating from the first side a second side of the ear, and a female portion for the second side of the ear including a housing having a bottom surface towards the second side of the ear including an internal opening configured to receive the upper portion of the protrusion, a retention portion configured to releasably retain the upper portion of the protrusion, a plurality of electronic components including a battery, a processor, and a temperature sensor, and a thermally conductive ring disposed upon on the bottom surface configured to be disposed against the second side, and wherein the thermally conductive ring is thermally coupled to the temperature sensor.
    Type: Application
    Filed: June 9, 2023
    Publication date: December 21, 2023
    Inventors: Yu-Chia CHANG, Cheng LUCKY, Cheng Pin HUANG
  • Patent number: 11848866
    Abstract: Systems and methods are described for effectively managing and maintaining a communication network by monitoring communications to detect a loop condition, and effectively route the communication to one or more destinations known to reduce or eliminate the occurrence of a looping condition.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: December 19, 2023
    Assignee: Comcast Cable Communications, LLC
    Inventors: Chia-Chang Li, Mohamed Barache, Robert Lambardia