Patents by Inventor Chia-Cheng Chen
Chia-Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12389662Abstract: A method of forming a semiconductor device includes etching trenches in a substrate to form fin structures, depositing a liner layer to line the trenches, filling the trenches with an insulating layer, performing an ion implantation process to the insulating layer, after performing the ion implantation process, recessing the insulating layer to form shallow trench isolation (STI) regions adjacent the fin structures, and forming a gate crossing the fin structures.Type: GrantFiled: May 17, 2022Date of Patent: August 12, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Szu-Ying Chen, Chia-Cheng Chen, Liang-Yin Chen, Sen-Hong Syue
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Publication number: 20250246586Abstract: An electronic package and a manufacturing method thereof are provided, in which a wiring structure electrically connected to a photonic structure is disposed on a surface of a part of the photonic structure, an electronic component is disposed on the wiring structure to be electrically connected to the wiring structure, and an optical element is disposed on a surface of another part of the photonic structure to be electrically connected to the photonic structure. Therefore, the photonic structure and the electronic component are placed relatively vertically on opposite sides of the wiring structure, thereby effectively reducing the layout area of the wiring structure to meet the demand for miniaturization.Type: ApplicationFiled: June 28, 2024Publication date: July 31, 2025Inventors: Ching-Chia CHEN, Wen-Jung TSAI, Ting-Yang CHOU, Chia-Cheng CHEN, Yu-Po WANG
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Patent number: 12374519Abstract: In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including integrated circuit dies; measuring a position of the wafer by measuring a position of an outer edge of the integrated circuit dies with a camera; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.Type: GrantFiled: August 27, 2021Date of Patent: July 29, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Cheng Chen, Chun-Liang Chen, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20250232985Abstract: A method of exposing a wafer to a high-tilt angle ion beam and an apparatus for performing the same are disclosed. In an embodiment, a method includes forming a patterned mask layer over a wafer, the patterned mask layer including a patterned mask feature; exposing the wafer to an ion beam, a surface of the wafer being tilted at a tilt angle with respect to the ion beam; and moving the wafer along a scan line with respect to the ion beam, a scan angle being defined between the scan line and an axis perpendicular to an axis of the ion beam, a difference between the tilt angle and the scan angle being less than 50°.Type: ApplicationFiled: April 7, 2025Publication date: July 17, 2025Inventors: Chia-Cheng Chen, Wei-Ting Chien, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Patent number: 12362010Abstract: A memory circuit includes a control circuit coupled to the word line driver circuit. The control circuit is configured to delay a leading or falling edge of a word line signal in response to at least a first clock signal. The control circuit includes a first clock circuit configured to generate a second clock signal in response to a first reset signal and a clock signal, and an adjustable delay circuit configured to adjust a delay between the second and third clock signal in response to the second clock signal and an enable signal. The third clock signal is a delayed version of the second clock signal. An amount of the delay between the second and third clock signal is based on a voltage difference between a first supply voltage having a first swing, and a second supply voltage having a second swing.Type: GrantFiled: July 26, 2023Date of Patent: July 15, 2025Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD, TSMC NANJING COMPANY, LIMITEDInventors: Luping Kong, Chia-Cheng Chen, Ching-Wei Wu, Jun Xie
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Patent number: 12354873Abstract: A semiconductor process system includes an ion source configured to bombard with a photoresist structure on a wafer. The semiconductor process system reduces a width of the photoresist structure by bombarding the photoresist structure with ions in multiple distinct ion bombardment steps having different characteristics.Type: GrantFiled: June 21, 2021Date of Patent: July 8, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Kai Yang, Yu-Tien Shen, Hsiang-Ming Chang, Chun-Yen Chang, Ya-Hui Chang, Wei-Ting Chien, Chia-Cheng Chen, Liang-Yin Chen
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Patent number: 12347681Abstract: A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.Type: GrantFiled: July 31, 2023Date of Patent: July 1, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Cheng Chen, Chun-Hung Wu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Chun-Yen Chang, Chih-Kai Yang, Yu-Tien Shen, Ya Hui Chang
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Patent number: 12340871Abstract: A circuit includes an array including a plurality of memory cells; a driver operatively coupled to the array and configured to provide an access signal controlling an access to one or more of the plurality of memory cells; and a timing controller operatively coupled to the driver. The timing controller is configured to: receive a control signal; and in response to the control signal transitioning from a first logic state to a second logic state, adjust a pulse width of the access signal within a single clock cycle containing a first phase and a second phase, wherein the first phase includes reading a first data bit stored in a first one of the one or more memory cells and the second phase includes writing a second data bit into the first memory cell.Type: GrantFiled: July 31, 2023Date of Patent: June 24, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Hung Chang, Chia-Cheng Chen, Ching-Wei Wu, Cheng Hung Lee
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Patent number: 12315753Abstract: A method of correcting a misalignment of a wafer on a wafer holder and an apparatus for performing the same are disclosed. In an embodiment, a semiconductor alignment apparatus includes a wafer stage; a wafer holder over the wafer stage; a first position detector configured to detect an alignment of a wafer over the wafer holder in a first direction; a second position detector configured to detect an alignment of the wafer over the wafer holder in a second direction; and a rotational detector configured to detect a rotational alignment of the wafer over the wafer holder.Type: GrantFiled: November 28, 2023Date of Patent: May 27, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Cheng Chen, Chih-Kai Yang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Patent number: 12293924Abstract: A method of exposing a wafer to a high-tilt angle ion beam and an apparatus for performing the same are disclosed. In an embodiment, a method includes forming a patterned mask layer over a wafer, the patterned mask layer including a patterned mask feature; exposing the wafer to an ion beam, a surface of the wafer being tilted at a tilt angle with respect to the ion beam; and moving the wafer along a scan line with respect to the ion beam, a scan angle being defined between the scan line and an axis perpendicular to an axis of the ion beam, a difference between the tilt angle and the scan angle being less than 50°.Type: GrantFiled: January 17, 2024Date of Patent: May 6, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Cheng Chen, Wei-Ting Chien, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20250132221Abstract: An electronic package is provided and includes: a carrier structure, an electronic component disposed on the carrier structure, a heat dissipation structure disposed on the electronic component, a heat conductor sandwiched between the electronic component and the heat dissipation structure, a first intermetallic compound layer formed between the heat dissipation structure and the heat conductor, and a second intermetallic compound layer formed between the heat conductor and the electronic component. Therefore, stable connections can be formed between the heat dissipation structure, the heat conductor and the electronic component via the first intermetallic compound layer and the second intermetallic compound layer to improve heat dissipation effect.Type: ApplicationFiled: June 26, 2024Publication date: April 24, 2025Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Dai-Fei LI, Liang-Yi HUNG, Chia-Cheng CHEN, Yu-Po WANG
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Publication number: 20250113551Abstract: A method includes: forming a stack of nanostructures over a substrate; forming a source/drain opening adjacent the stack of nanostructures; forming a semiconductor layer in the source/drain opening; forming an amorphous semiconductor layer by performing an ion implantation on the semiconductor layer; and forming a recrystallized source/drain by annealing the amorphous semiconductor layer.Type: ApplicationFiled: January 4, 2024Publication date: April 3, 2025Inventors: Chia-Cheng CHEN, Sih-Jie LIU, Liang-Yin CHEN, Chi On CHUI
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Publication number: 20250105068Abstract: An electronic package and a manufacturing method thereof are provided, in which a first barrier body and a second barrier body are disposed respectively, and a heat dissipation structure is formed with a hole thereon. Thereby, gas in the heat dissipation structure can be discharged via the hole, so as to prevent the gas from remaining in a thermal conductive layer and affecting the heat dissipation effect.Type: ApplicationFiled: July 2, 2024Publication date: March 27, 2025Inventors: Chuan-Shun LI, Pin-Jing SU, Liang-Yi HUNG, Chia-Cheng CHEN, Yu-Po WANG
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Publication number: 20250107184Abstract: A semiconductor device structure and methods of forming the same are described. The method includes forming a fin structure from a substrate, depositing a first semiconductor material on a first semiconductor layer of the fin structure, depositing a second semiconductor material on the first semiconductor material, depositing an interlayer dielectric layer over the second semiconductor material, forming an opening in the interlayer dielectric layer to expose the second semiconductor material, and performing a dopant implantation process to form a doped region. The doped region includes a first portion of the second semiconductor material. Then, the method further includes performing an amorphization process to form an amorphous region, and the amorphous region includes a second portion of the second semiconductor material. The method further includes performing an annealing process to recrystallize the amorphous region.Type: ApplicationFiled: January 3, 2024Publication date: March 27, 2025Inventors: Wen-Yen CHEN, Min-Tsang LI, Liang-Yin CHEN, Chi On CHUI, Chia-Cheng CHEN
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Publication number: 20250095704Abstract: A memory device includes: a first array of memory cells; a second array of tracking cells, the second array being configured to emulate the first array; a first word line coupled to corresponding ones of the memory cells in a corresponding one of rows of the first array and to the tracking cells; a second word line configured to emulate the first word line; a first adjust circuit coupled to the first word line; a second adjust circuit coupled to the second word line; and an adjust-timing circuit coupled to the second adjust circuit.Type: ApplicationFiled: September 21, 2023Publication date: March 20, 2025Inventors: Luping KONG, Chia-Cheng CHEN, Ching-Wei WU, Jun XIE
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Publication number: 20250044708Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.Type: ApplicationFiled: October 18, 2024Publication date: February 6, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Gun LIU, Huicheng CHANG, Chia-Cheng CHEN, Jyu-Horng SHIEH, Liang-Yin CHEN, Shu-Huei SUEN, Wei-Liang LIN, Ya Hui CHANG, Yi-Nien SU, Yung-Sung YEN, Chia-Fong CHANG, Ya-Wen YEH, Yu-Tien SHEN
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Publication number: 20250037751Abstract: A memory device includes a memory array comprising a plurality of word lines, the plurality of word lines operatively coupled to a plurality of sets of memory cells, respectively. The memory device includes a controller operatively coupled to the memory array, and comprising an adaptive tracking circuit. The adaptive tracking circuit is configured to: receive a first signal conducted through a first tracking line; receive an address signal indicating one of the word lines to be asserted; and adjust, based on the address signal, a timing of a transition edge of a second signal conducted through a second tracking line.Type: ApplicationFiled: October 2, 2023Publication date: January 30, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Cheng Chen, Yu Jie Hsiao, Ching-Wei Wu
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Publication number: 20250022501Abstract: A circuit and method for establishing a balanced negative voltage to a near-end and far-end of a bitline having a plurality of memory cells connected to the bitline is disclosed. A MOS capacitor and a metal capacitor are connected in parallel. The MOS capacitor is connected to the near-end of the bitline through a first switch transistor. The metal capacitor is connected to the near-end of the bitline through the first switch transistor and the far end of the bitline through a second switch transistor. A falling negative boost voltage is applied to the MOS capacitor and the metal capacitor. When the switch transistors are turned on during a write operation, the MOS capacitor and the metal capacitor are both coupled to the voltage at the near-end and far-end and drive the voltage to approximately equal the boost voltage, thereby providing a balanced voltage to the bitline.Type: ApplicationFiled: July 15, 2024Publication date: January 16, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: JUI-CHE TSAI, CHIA-EN HUANG, CHIA-CHENG CHEN, YIH WANG
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Patent number: 12191174Abstract: In an embodiment, a pattern transfer processing chamber includes a pattern transfer processing chamber and a loading area external to the pattern transfer processing chamber. The loading area is configured to transfer a wafer to or from the pattern transfer processing chamber. The loading area comprises a first region including a loadport, a second region including a load-lock between the first region and the pattern transfer processing chamber, and an embedded baking chamber configured to heat a patterned photoresist on the wafer.Type: GrantFiled: April 14, 2022Date of Patent: January 7, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Cheng Chen, Chih-Kai Yang, Chun-Liang Chen, Wei-Ting Chien, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Patent number: D1078418Type: GrantFiled: August 1, 2023Date of Patent: June 10, 2025Assignee: Stanley Black & Decker MEA FZEInventors: Yen Ting Wu, Ko Han Chen, Chia Cheng Chen, Yi Tung Chan, ChihChiang Lee