Patents by Inventor Chia-Cheng Chen

Chia-Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978677
    Abstract: In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including alignment marks; measuring a position of the wafer by measuring positions of the alignment marks with one or more cameras; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Cheng Chen, Chih-Kai Yang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20240145389
    Abstract: A semiconductor chip includes a first intellectual property block. There are a second intellectual property block and a third intellectual property block around the first intellectual property block. There is a multiple metal layer stack over the first intellectual property block, the second intellectual property block, and the third intellectual property block. An interconnect structure is situated in the upper portion of the multiple metal layer stack. The interconnect structure is configured for connecting the first intellectual property block and the second intellectual property block. In addition, at least a part of the interconnect structure extends across and over the third intellectual property block.
    Type: Application
    Filed: July 28, 2023
    Publication date: May 2, 2024
    Inventors: Li-Chiu WENG, Yew Teck TIEO, Ming-Hsuan WANG, Chia-Cheng CHEN, Wei-Yi CHANG, Jen-Hang YANG, Chien-Hsiung HSU
  • Publication number: 20240144098
    Abstract: Aspects of the present disclosure provide an automated labeling system. For example, the automated labeling system can include an automated labeling module (ALM) configured to receive wireless signals and ground truth of learning object and label the wireless signals with the ground truth when receiving the ground truth to generate labeled training data. The automated labeling system can also include a training database coupled to the ALM. The training database can be configured to store the labeled training data.
    Type: Application
    Filed: October 16, 2023
    Publication date: May 2, 2024
    Applicant: MEDIATEK INC.
    Inventors: Chao Peng WANG, Chia-Da LEE, Po-Yu CHEN, Hsiao-Chien CHIU, Yi-Cheng LU
  • Publication number: 20240134268
    Abstract: A mask for use in a semiconductor lithography process includes a substrate, a mask pattern disposed on the substrate, and a light absorbing border surrounding the mask pattern. The light absorbing border is inset from at least two edges of the substrate to define a peripheral region outside of the light absorbing border. In some designs, a first peripheral region extends from an outer perimeter of the light absorbing border to a first edge of the substrate, and a second peripheral region that extends from the outer perimeter of the light absorbing border to a second edge of the substrate, where the first edge of the substrate and the second edge of the substrate are on opposite sides of the mask pattern.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Inventors: Chien-Cheng Chen, Huan-Ling Lee, Ta-Cheng Lien, Chia-Jen Chen, Hsin-Chang Lee
  • Publication number: 20240124844
    Abstract: The present disclosure provides a method for preparing a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors, the composition prepared by the method, and use of the composition for treating arthritis. The composition of the present disclosure achieves the effect of treating arthritis through various efficacy experiments.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 18, 2024
    Inventors: Chia-Hsin Lee, Po-Cheng Lin, Yong-Cheng Kao, Ming-Hsi Chuang, Chun-Hung Chen, Chao-Liang Chang, Kai-Ling Zhang
  • Patent number: 11962847
    Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: April 16, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chia-Hao Chang, You-Tsai Jeng, Kai-Wen Yeh, Yi-Cheng Chen, Te-Chuan Wang, Kai-Wen Cheng, Chin-Lung Lin, Tai-Lai Tung, Ko-Yin Lai
  • Publication number: 20240121935
    Abstract: Methods for fabricating semiconductor structures are provided. An exemplary method includes forming a first transistor structure and a second transistor structure over a substrate, wherein each transistor structure includes at least one nanosheet. The method further includes depositing a metal over each transistor structure and around each nanosheet; depositing a coating over the metal; depositing a mask over the coating; and patterning the mask to define a patterned mask, wherein the patterned mask lies over a masked portion of the coating and the second transistor structure, and wherein the patterned mask does not lie over an unmasked portion of the coating and the first transistor structure. The method further includes etching the unmasked portion of the coating and the metal over the first transistor structure using a dry etching process with a process pressure of from 30 to 60 (mTorr).
    Type: Application
    Filed: January 18, 2023
    Publication date: April 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Y.L. Cheng, Tzu-Wen Pan, Yu-Hsien Lin, Ryan Chia-Jen Chen
  • Publication number: 20240118352
    Abstract: A method for determining a road type includes measuring, for a preset period, a magnetic field of an environment in which an electronic device is located to obtain a plurality of magnetic field values, calculating an absolute value of a difference between every two adjacent magnetic field values among the magnetic field values sorted in chronological order, calculating an average of the absolute values related to the magnetic field values to serve as a variation value for the environment, determining whether the variation value is smaller than a predetermined threshold value, determining that the environment is a surface road when the determination result is affirmative, and determining that the environment is a non-surface road when the determination result is negative.
    Type: Application
    Filed: November 23, 2022
    Publication date: April 11, 2024
    Inventors: Chia-Cheng WANG, Jyh-Cheng CHEN, Yu-Xin XIAO
  • Publication number: 20240115616
    Abstract: The present disclosure provides a method for treating liver cirrhosis by using a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors. The composition of the present disclosure achieves the effect of treating liver cirrhosis through various efficacy experiments.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 11, 2024
    Inventors: Po-Cheng Lin, Pi-Chun Huang, Zih-Han Hong, Ming-Hsi Chuang, Yi-Chun Lin, Chia-Hsin Lee, Chun-Hung Chen, Chao-Liang Chang, Kai-Ling Zhang
  • Patent number: 11955507
    Abstract: A light-emitting device, including a first type semiconductor layer, a patterned insulating layer, a light-emitting layer, and a second type semiconductor layer, is provided. The patterned insulating layer covers the first type semiconductor layer and has a plurality of insulating openings. The insulating openings are separated from each other. The light-emitting layer is located in the plurality of insulating openings and covers a portion of the first type semiconductor layer. The second type semiconductor layer is located on the light-emitting layer.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: April 9, 2024
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Hsin-Hung Li, Wei-Syun Wang, Chih-Chiang Chen, Yu-Cheng Shih, Cheng-Chan Wang, Chia-Hsin Chung, Ming-Jui Wang, Sheng-Ming Huang
  • Patent number: 11955397
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: April 9, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shin-Cheng Lin, Cheng-Wei Chou, Ting-En Hsieh, Yi-Han Huang, Kwang-Ming Lin, Yung-Fong Lin, Cheng-Tao Chou, Chi-Fu Lee, Chia-Lin Chen, Shu-Wen Chang
  • Patent number: 11948949
    Abstract: In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yuan Chen, Ching-Chun Wang, Hsiao-Hui Tseng, Jen-Cheng Liu, Jhy-Jyi Sze, Shyh-Fann Ting, Wei Chuang Wu, Yen-Ting Chiang, Chia Ching Liao, Yen-Yu Chen
  • Publication number: 20240096677
    Abstract: A method of correcting a misalignment of a wafer on a wafer holder and an apparatus for performing the same are disclosed. In an embodiment, a semiconductor alignment apparatus includes a wafer stage; a wafer holder over the wafer stage; a first position detector configured to detect an alignment of a wafer over the wafer holder in a first direction; a second position detector configured to detect an alignment of the wafer over the wafer holder in a second direction; and a rotational detector configured to detect a rotational alignment of the wafer over the wafer holder.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Chia-Cheng Chen, Chih-Kai Yang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20240097051
    Abstract: A Schottky diode includes a substrate, a first drift region in the substrate, a second drift region in the substrate, a first dielectric layer disposed over the substrate, a first doped region in the first drift region, a second doped region in the second drift region, a third doped region in the first drift region, and a metal field plate disposed over the first dielectric layer. The first drift region and the first doped region include a first conductivity type. The second drift region, the second doped region and third doped region include a second conductivity type complementary to the first conductivity type. The first dielectric layer overlaps a portion of the first drift region and a portion of the second drift region. The second doped region is separated from the first doped region.
    Type: Application
    Filed: January 16, 2023
    Publication date: March 21, 2024
    Inventors: GUAN-YI LI, CHIA-CHENG HO, CHAN-YU HUNG, FEI-YUN CHEN
  • Publication number: 20240094625
    Abstract: A method of making a semiconductor device includes forming at least one fiducial mark on a photomask. The method further includes defining a pattern including a plurality of sub-patterns on the photomask in a pattern region. The defining the pattern includes defining a first sub-pattern of the plurality of sub-patterns having a first spacing from a second sub-pattern of the plurality of sub-patterns, wherein the first spacing is different from a second spacing between the second sub-pattern and a third sub-pattern of the plurality of sub-patterns.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Hsin-Chang LEE, Ping-Hsun LIN, Chih-Cheng LIN, Chia-Jen CHEN
  • Patent number: 11936299
    Abstract: A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region. The transistor further includes a source/drain (S/D) in the substrate adjacent to the gate structure. The transistor further includes a lightly doped drain (LDD) region adjacent to the S/D, wherein a dopant concentration in the first LDD is less than a dopant concentration in the S/D. The transistor further includes a doping extension region adjacent the LDD region, wherein the doping extension region extends farther under the gate structure than the LDD region, and a maximum depth of the doping extension region is 10-times to 30-times greater than a maximum depth of the LDD.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chu Fu Chen, Chi-Feng Huang, Chia-Chung Chen, Chin-Lung Chen, Victor Chiang Liang, Chia-Cheng Pao
  • Patent number: 11931456
    Abstract: A pharmaceutical composition containing a mixed polymeric micelle and a drug enclosed in the micelle, in which the mixed polymeric micelle, 1 to 1000 nm in size, includes an amphiphilic block copolymer and a lipopolymer. Also disclosed are preparation of the pharmaceutical composition and use thereof for treating cancer.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: March 19, 2024
    Assignee: MegaPro Biomedical Co. Ltd.
    Inventors: Ming-Cheng Wei, Yuan-Hung Hsu, Wen-Yuan Hsieh, Chia-Wen Huang, Chih-Lung Chen, Jhih-Yun Jian, Shian-Jy Wang
  • Publication number: 20240088195
    Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a shallow trench isolation, and a color filter layer. The radiation sensing member is in the semiconductor substrate. An interface between the radiation sensing member and the semiconductor substrate includes a direct band gap material. The shallow trench isolation is in the semiconductor substrate and surrounds the radiation sensing member. The color filter layer covers the radiation sensing member.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yu WEI, Yen-Liang LIN, Kuo-Cheng LEE, Hsun-Ying HUANG, Hsin-Chi CHEN
  • Patent number: 11915942
    Abstract: A method of exposing a wafer to a high-tilt angle ion beam and an apparatus for performing the same are disclosed. In an embodiment, a method includes forming a patterned mask layer over a wafer, the patterned mask layer including a patterned mask feature; exposing the wafer to an ion beam, a surface of the wafer being tilted at a tilt angle with respect to the ion beam; and moving the wafer along a scan line with respect to the ion beam, a scan angle being defined between the scan line and an axis perpendicular to an axis of the ion beam, a difference between the tilt angle and the scan angle being less than 50°.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Cheng Chen, Wei-Ting Chien, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Patent number: D1023802
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: April 23, 2024
    Assignee: TRON FUTURE TECH INC.
    Inventors: Yu-Jiu Wang, Chia-Cheng Kung, Yu-Ju Chen, Boon How Teoh