Patents by Inventor Chia-Cheng Chen

Chia-Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11570081
    Abstract: A multi-member Bluetooth device for communicating data with a remote Bluetooth device is disclosed including: a main Bluetooth circuit and an auxiliary Bluetooth circuit. In the period during which the auxiliary Bluetooth circuit operates at a sniffing mode, the auxiliary Bluetooth circuit sniffs packets transmitted from the remote Bluetooth device while the main Bluetooth circuit receives packets issued from the remote Bluetooth device, and the auxiliary Bluetooth circuit switches from the sniffing mode to a relay mode if the throughput of packets sniffed by the auxiliary Bluetooth circuit is lower than a predetermined threshold. In the period during which the auxiliary Bluetooth circuit operates at the relay mode, the main Bluetooth circuit receives packets transmitted from the remote Bluetooth device and forwards the received packets to the auxiliary Bluetooth circuit, and the auxiliary Bluetooth circuit does not sniff packets issued from the remote Bluetooth device.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: January 31, 2023
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yi-Cheng Chen, Kuan-Chung Huang, Chia Chun Hung, Hou Wei Lin
  • Publication number: 20230016605
    Abstract: A method of fabricating a semiconductor device is described. A plurality of fins is formed over a substrate. Dummy gates are formed patterned over the fins, each dummy gate having a spacer on sidewalls of the patterned dummy gates. Recesses are formed in the fins using the patterned dummy gates as a mask. A passivation layer is formed over the fins and in the recesses in the fins. The passivation layer is patterned to leave a remaining passivation layer only in some of the recesses in the fins. Source and drain regions are epitaxially formed only in the recesses in the fins without the remaining passivation layer.
    Type: Application
    Filed: July 15, 2021
    Publication date: January 19, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Shih-Yao Lin, Chao-Cheng Chen, Chih-Han Lin, Chen-Ping Chen, Ming-Ching Chang, Chia-Hao Yu, Hsiao Wen Lee
  • Publication number: 20230016381
    Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate; a gate structure engaging with the semiconductor fin. The semiconductor structure also includes an interlayer dielectric (ILD) layer disposed over the substrate and adjacent to the gate structure, where a top surface of the gate structure is below a top surface of the ILD layer; a first metal layer in direct contact with a top surface of the gate structure; a second metal layer disposed over the first metal layer, where the first metal layer is disposed on bottom and sidewall surfaces of the second metal layer, where the bottom surface of the second metal layer has a concave profile, and where the second metal layer differs from the first metal layer in composition; and a gate contact disposed over the second metal layer.
    Type: Application
    Filed: May 6, 2022
    Publication date: January 19, 2023
    Inventors: Wei-Cheng Wang, Shih-Hang Chiu, Kuan-Ting Liu, Chi On Chui, Chia-Wei Chen, Jian-Hao Chen
  • Publication number: 20230014253
    Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, a gate structure extending on the fin in a second direction, and a seal layer located on the sidewall of the gate structure. A first peak carbon concentration is disposed in the seal layer. A first spacer layer is located on the seal layer. A second peak carbon concentration is disposed in the first spacer layer. A second spacer layer is located on the first spacer layer.
    Type: Application
    Filed: August 2, 2021
    Publication date: January 19, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shi-You Liu, Shih-Cheng Chen, Chia-Wei Chang, Chia-Ming Kuo, Tsai-Yu Wen, Yu-Ren Wang
  • Publication number: 20230013260
    Abstract: A method for lithographically patterning a photoresist is provided. The method includes receiving a wafer with the photoresist and exposing the photoresist using an extreme ultraviolet (EUV) radiation reflected by an EUV mask. The EUV mask includes a substrate, a reflective multilayer stack on the substrate, a capping layer on the reflective multilayer stack, a patterned absorber layer on the capping layer. The patterned absorber layer includes a matrix metal and an interstitial element occupying interstitial sites of the matrix metal, and a size ratio of the interstitial element to the matrix metal is from about 0.41 to about 0.59.
    Type: Application
    Filed: April 8, 2022
    Publication date: January 19, 2023
    Inventors: Yi-Jhih LIN, Pei-Cheng HSU, Ta-Cheng LIEN, Chia-Jen CHEN, Hsin-Chang LEE
  • Publication number: 20230011763
    Abstract: The present application provides a gesture determining method and an electronic device. The gesture determining method includes: sensing a control gesture through at least one motion sensor, and correspondingly generating sensing data; sequentially segmenting the sensing data into a plurality of streaming windows according to a unit of time, each streaming window including a group of sensing values; determining whether a sensing value in a streaming window is greater than a critical value, and triggering subsequent gesture recognition when the sensing value is greater than the critical value; and performing a recognition operation on the streaming window by using a gesture recognition model to consecutively output a recognition result; and determining whether the recognition result meets an output condition, and outputting a predicted gesture corresponding to the recognition result when the recognition result meets the output condition.
    Type: Application
    Filed: June 20, 2022
    Publication date: January 12, 2023
    Inventors: Shih-Chieh Liao, Chin-Hao Chang, Shih-Chuan Chiu, Yi-Nan Lee, Chia-Hao Kang, Wei-Cheng Chen, Tzu-Hung Chuang
  • Publication number: 20230009031
    Abstract: A method includes determining a target etching depth for etching a plurality of dielectric regions in a wafer. The wafer includes a plurality of protruding semiconductor fins and the plurality of dielectric regions between the plurality of protruding semiconductor fins. The method further includes etching the plurality of dielectric regions, projecting a light beam on the wafer, and generating a spectrum from a reflected light reflected from the wafer, determining an end point for etching based on the spectrum. The end point is an expected time point. The plurality of dielectric regions are etched to the target etching depth. The etching of the plurality of dielectric regions is stopped at the end point.
    Type: Application
    Filed: January 25, 2022
    Publication date: January 12, 2023
    Inventors: Jui Fu Hsieh, Chia-Chi Yu, Chih-Teng Liao, Yi-Jen Chen, Chia-Cheng Tai
  • Publication number: 20230010065
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure. The gate structure includes a gate dielectric layer, an n-type work function layer embedded in the gate dielectric layer, a dielectric capping layer embedded in the n-type work function layer, and a p-type work function layer embedded in the dielectric capping layer. A top surface of the gate structure exposes the n-type work function layer, the dielectric capping layer, and the p-type work function layer. The semiconductor structure also includes a first metal cap on the n-type work function layer and a second metal cap on the p-type work function layer. The first metal cap is spaced apart from the second metal cap. without formed on the dielectric capping layer.
    Type: Application
    Filed: June 7, 2022
    Publication date: January 12, 2023
    Inventors: Shih-Hang Chiu, Chung-Chiang Wu, Wei-Cheng Wang, Chia-Wei Chen, Jian-Hao Chen, Kuan-Ting Liu, Chi On Chui
  • Publication number: 20230010952
    Abstract: A semiconductor device includes stacks of nano-structures that each extend in a first horizontal direction. The stacks each extend in a vertical direction and are separated from one another in a second horizontal direction. A first gate is disposed over a first subset of the stacks. A second gate is disposed over a second subset of the stacks. A first conductive capping layer is disposed over a substantial entirety of an upper surface of the first gate. A second conductive capping layer is disposed over a substantial entirety of an upper surface of the second gate. A dielectric structure is disposed between the first gate and the second gate in the second horizontal direction. The dielectric structure physically and electrically separates the first gate and the second gate. An upper surface of the dielectric structure is substantially free of having the first or second conductive capping layers disposed thereon.
    Type: Application
    Filed: May 5, 2022
    Publication date: January 12, 2023
    Inventors: Chia-Wei Chen, Wei Cheng Hsu, Hui-Chi Chen, Jian-Hao Chen, Kuo-Feng Yu, Shih-Hang Chiu, Wei-Cheng Wang, Yen-Ju Chen, Chun-Chih Cheng
  • Patent number: 11553273
    Abstract: A passive diaphragm assembly includes a counterweight member, a first diaphragm and a second diaphragm. The first diaphragm and the second diaphragm are spaced apart from each other, are connected respectively to opposite ends of the counterweight member, and cooperate with the counterweight member to define an air space thereamong.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: January 10, 2023
    Assignee: Jabil Circuit (Singapore) Pte. Ltd.
    Inventors: Wen Hong Wang, Ching Feng Lin, Chia Chien Chen, Po-Cheng Huang, Shih-Hsien Yang
  • Patent number: 11541007
    Abstract: A pharmaceutical composition containing a mixed polymeric micelle and a drug enclosed in the micelle, in which the mixed polymeric micelle, 1 to 1000 nm in size, includes an amphiphilic block copolymer and a lipopolymer. Also disclosed are preparation of the pharmaceutical composition and use thereof for treating cancer.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: January 3, 2023
    Assignee: MegaPro Biomedical Co., Ltd.
    Inventors: Ming-Cheng Wei, Yuan-Hung Hsu, Wen-Yuan Hsieh, Chia-Wen Huang, Chih-Lung Chen, Jhih-Yun Jian, Shian-Jy Wang
  • Patent number: 11545792
    Abstract: An electrical plug connector includes a metallic shell, an insulated member, plug terminals, and grounding members. The insulated member is in the metallic shell. The plug terminals are held in the insulated member. The grounding members and the insulated member are molded as a one-piece member, thereby reducing the production steps as well as reducing production of defect products. Moreover, the first curved contact portion extends toward the metallic shell and effectively contacts the metallic shell, and the second curved contact portion extends toward the ground terminal and effectively contacts the ground terminal.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: January 3, 2023
    Assignee: ADVANCED-CONNECTEK INC.
    Inventors: Ming-Yung Chang, Chia-Cheng He, Mao-Sheng Chen
  • Publication number: 20220415606
    Abstract: In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including integrated circuit dies; measuring a position of the wafer by measuring a positions of an outer edge of the integrated circuit dies with a camera; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.
    Type: Application
    Filed: August 27, 2021
    Publication date: December 29, 2022
    Inventors: Chia-Cheng Chen, Chun-Liang Chen, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20220415719
    Abstract: In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including alignment marks; measuring a position of the wafer by measuring positions of the alignment marks with one or more cameras; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.
    Type: Application
    Filed: August 27, 2021
    Publication date: December 29, 2022
    Inventors: Chia-Cheng Chen, Chih-Kai Yang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20220406592
    Abstract: A method of forming a semiconductor device includes forming a photoresist over a target layer, where the target layer includes a substrate. The photoresist is patterned to form a patterned photoresist. Scum remains between portions of the patterned photoresist. The substrate is tilted relative to a direction of propagation of an ion beam. An ion treatment is performed on the scum. A pattern of the patterned photoresist is transferred to the target layer.
    Type: Application
    Filed: February 21, 2022
    Publication date: December 22, 2022
    Inventors: Chun-Hung Wu, Chia-Cheng Chen, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20220406629
    Abstract: In an embodiment, a pattern transfer processing chamber includes a pattern transfer processing chamber and a loading area external to the pattern transfer processing chamber. The loading area is configured to transfer a wafer to or from the pattern transfer processing chamber. The loading area comprises a first region including a loadport, a second region including a load-lock between the first region and the pattern transfer processing chamber, and an embedded baking chamber configured to heat a patterned photoresist on the wafer.
    Type: Application
    Filed: April 14, 2022
    Publication date: December 22, 2022
    Inventors: Chia-Cheng Chen, Chih-Kai Yang, Chun-Liang Chen, Wei-Ting Chien, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11532662
    Abstract: A method includes providing a semiconductor substrate having a front side surface and a back side surface opposite to the front side surface. A photosensitive region of the semiconductor substrate is etched to form a recess. A semiconductor material is deposited on the semiconductor substrate to form a radiation sensing member filling the recess. The semiconductor material has an optical band gap energy smaller than 1.77 eV. A device layer is formed over the front side surface of the semiconductor substrate and the radiation sensing member. A trench isolation is formed in an isolation region of the semiconductor substrate and extending from the back side surface of the semiconductor substrate.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yu Wei, Yen-Liang Lin, Kuo-Cheng Lee, Hsun-Ying Huang, Hsin-Chi Chen
  • Patent number: 11526081
    Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Ming Chang, Wen Lo, Chun-Hung Liu, Chia-Hua Chang, Hsin-Wei Wu, Ta-Wei Ou, Chien-Chih Chen, Chien-Cheng Chen
  • Publication number: 20220387756
    Abstract: A urinary catheter conveying device includes a sleeve member, a conveying assembly and a controller. The sleeve member is for sleeving onto a glans of a penis and has a guiding hole to be registered with an external urethral orifice of the glans. The conveying assembly includes a casing removably mounted to the sleeve member, and a conveying mechanism for advancing the urinary catheter to the guiding hole such that the urinary catheter is inserted into the external urethral orifice. The controller controls the conveying mechanism to advance the urinary catheter to the guiding hole. A urinary catheterization system and a method of using the urinary catheterization system are also disclosed.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 8, 2022
    Inventors: Chung-Cheng Wang, Yung-Ping Wang, Yi-Yuan Chen, Chia-Ming Hsu, Ming-Chien Chiu, Chia-Ch Lin
  • Publication number: 20220390827
    Abstract: A lithography mask including a substrate, a phase shift layer on the substrate and an etch stop layer is provided. The phase shift layer is patterned and the substrate is protected from etching by the etch stop layer. The etch stop layer can be a material that is semi-transmissive to light used in photolithography processes or it can be transmissive to light used in photolithography processes.
    Type: Application
    Filed: April 8, 2022
    Publication date: December 8, 2022
    Inventors: Chien-Cheng Chen, Huan-Ling Lee, Ta-Cheng Lien, Chia-Jen Chen, Hsin-Chang Lee