Patents by Inventor Chia-Chun Yeh
Chia-Chun Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9564537Abstract: Disclosed herein is a method for manufacturing an array substrate. The method includes forming a source electrode and a drain electrode on a substrate. A semiconductor layer, an organic insulating layer, and a gate electrode layer are sequentially formed to cover the substrate, the source electrode, and the drain electrode. A patterned photoresist layer is formed on the gate electrode layer. The exposed portion of the gate electrode layer, and a portion of the organic insulative layer and a portion of the semiconductor layer thereunder are removed to form a gate electrode. An organic passivation layer is formed on the gate electrode, the source electrode, and the drain electrode. The organic passivation layer has a contact window to expose a portion of the drain electrode. A pixel electrode is formed on the organic passivation layer and the exposed portion of the drain electrode.Type: GrantFiled: September 21, 2015Date of Patent: February 7, 2017Assignee: E Ink Holdings Inc.Inventors: Wei-Chou Lan, Ted-Hong Shinn, Henry Wang, Chia-Chun Yeh
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Patent number: 9513670Abstract: A touch panel including a substrate, at least one touch-sensing unit, at least one connecting pad, at least a testing line, at least one ESD protection circuit, and a first isolation layer is provided. The touch-sensing unit is disposed on the substrate. The connecting pad is disposed on the substrate and electrically connected to the touch-sensing unit. The testing line is disposed on the substrate, electrically connected to the connecting pad, and extends to at least an edge of the substrate. The ESD protection circuit is disposed in the edge of the substrate and electrically connected to a ground voltage, wherein a vertical projection of the testing line to the substrate and that of the ESD protection circuit to the substrate is at least partially overlapped. The first isolation layer is disposed between the testing line and the ESD protection circuit.Type: GrantFiled: January 28, 2014Date of Patent: December 6, 2016Assignee: AU OPTRONICS CORPORATIONInventors: Yi-Chi Chen, Chia-Chun Yeh, Chien-Yu Chen, Yi-Ling Lin, Yi-Hsin Lin
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Patent number: 9443986Abstract: A thin file transistor includes a gate electrode, a source electrode, a drain electrode, a gate-insulating layer, and an oxide semiconductor layer. The oxide semiconductor layer includes indium-gallium-zinc oxide with a formula of InxGayZnzOw, in which x, y and z satisfy the following formulas 1.5?(y/x)?2 and 1.5?(y/z)?2. The gate-insulating layer is positioned between the gate electrode and the oxide semiconductor layer. The source electrode and the drain electrode are respectively connected to two different sides of the oxide semiconductor layer.Type: GrantFiled: March 4, 2014Date of Patent: September 13, 2016Assignee: E Ink Holdings Inc.Inventors: Chih-Hsuan Wang, Chia-Chun Yeh, Ted-Hong Shinn
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Publication number: 20160116779Abstract: A touch display panel including an active device array substrate, an opposite substrate and a liquid crystal layer is provided. The active device array substrate includes a first substrate, a black matrix, a touch-sensing device layer, a dielectric layer and an active device array layer. The black matrix is disposed on the first substrate. The touch-sensing device layer is disposed on the first substrate to cover a portion of the black matrix. The dielectric layer covers the touch-sensing device layer. The active device array layer is disposed on the dielectric layer. The touch-sensing device layer and the active device array substrate are located at two opposite sides of the dielectric layer. The liquid crystal layer is disposed between the active device array layer and the opposite substrate. Moreover, a fabricating method of the touch display panel is also provided.Type: ApplicationFiled: December 14, 2015Publication date: April 28, 2016Inventors: Chia-Chun Yeh, Yu-Feng Chien, Wen-Rei Guo, Hung-Wen Chou, Chin-Chuan Liu, Po-Yuan Liu
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Patent number: 9261265Abstract: A backlight display device includes a pixel region, a light-emitting region, a control element, a plurality of first flexible printed circuit board (FPCB) contacts, and a plurality of first driving circuits. The pixel region has a first edge, a second edge opposite to the first edge, a third edge, and a fourth edge opposite to the third edge. A corner region is formed between the first edge and the fourth edge. The light-emitting region is located on the corner region of the pixel region. The control element is located on the corner region of the pixel region and between the light-emitting region and the first edge. The first FPCB contacts are located on the second edge. Each of the first driving circuits is electrically connected to one of the first FPCB contacts and the control element.Type: GrantFiled: May 29, 2015Date of Patent: February 16, 2016Assignee: E Ink Holdings Inc.Inventors: Shu-Ping Yan, Pei-Lin Huang, Wei-Chou Lan, Chia-Chun Yeh
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Publication number: 20160033120Abstract: A backlight display device includes a pixel region, a light-emitting region, a control element, a plurality of first flexible printed circuit board (FPCB) contacts, and a plurality of first driving circuits. The pixel region has a first edge, a second edge opposite to the first edge, a third edge, and a fourth edge opposite to the third edge. A corner region is formed between the first edge and the fourth edge. The light-emitting region is located on the corner region of the pixel region. The control element is located on the corner region of the pixel region and between the light-emitting region and the first edge. The first FPCB contacts are located on the second edge. Each of the first driving circuits is electrically connected to one of the first FPCB contacts and the control element.Type: ApplicationFiled: May 29, 2015Publication date: February 4, 2016Inventors: Shu-Ping YAN, Pei-Lin HUANG, Wei-Chou LAN, Chia-Chun YEH
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Patent number: 9239653Abstract: A touch panel includes a substrate, a touch-sensing circuit, and fan-out traces. The substrate has a touch-sensing region and an adjoined peripheral region. The touch-sensing circuit is disposed on the touch-sensing region. The fan-out traces are disposed on the peripheral region and electrically connected to the touch-sensing circuit. Each fan-out trace includes a first conductive line, a first dielectric layer and a second conductive line. The first conductive line is disposed on the peripheral region. The first dielectric layer is disposed on the peripheral region to cover the first conductive line, and has at least one contact window located above the first conductive line. The second conductive line is disposed on the first dielectric layer, wherein the first and the second conductive line of the same fan-out trace have the same pattern and are electrically connected through the contact window.Type: GrantFiled: August 6, 2012Date of Patent: January 19, 2016Assignee: Au Optronics CorporationInventors: Wen-Chi Chuang, Chia-Chun Yeh, Yu-Ching Huang
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Publication number: 20160013322Abstract: Disclosed herein is a method for manufacturing an array substrate. The method includes forming a source electrode and a drain electrode on a substrate. A semiconductor layer, an organic insulating layer, and a gate electrode layer are sequentially formed to cover the substrate, the source electrode, and the drain electrode. A patterned photoresist layer is formed on the gate electrode layer. The exposed portion of the gate electrode layer, and a portion of the organic insulative layer and a portion of the semiconductor layer thereunder are removed to form a gate electrode. An organic passivation layer is formed on the gate electrode, the source electrode, and the drain electrode. The organic passivation layer has a contact window to expose a portion of the drain electrode. A pixel electrode is formed on the organic passivation layer and the exposed portion of the drain electrode.Type: ApplicationFiled: September 21, 2015Publication date: January 14, 2016Inventors: Wei-Chou LAN, Ted-Hong SHINN, Henry WANG, Chia-Chun YEH
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Publication number: 20150380445Abstract: Disclosed herein is a method for manufacturing an array substrate. The method includes forming a source electrode and a drain electrode on a substrate. A semiconductor layer, an organic insulating layer, and a gate electrode layer are sequentially formed to cover the substrate, the source electrode, and the drain electrode. A patterned photoresist layer is formed on the gate electrode layer. The exposed portion of the gate electrode layer, and a portion of the organic insulative layer and a portion of the semiconductor layer thereunder are removed to form a gate electrode. An organic passivation layer is formed on the gate electrode, the source electrode, and the drain electrode. The organic passivation layer has a contact window to expose a portion of the drain electrode. A pixel electrode is formed on the organic passivation layer and the exposed portion of the drain electrode.Type: ApplicationFiled: September 4, 2015Publication date: December 31, 2015Inventors: Wei-Chou LAN, Ted-Hong SHINN, Henry WANG, Chia-Chun YEH
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Patent number: 9223447Abstract: A touch panel including a substrate, a light shielding layer, a touch sensing device layer, a protective layer, and at least one light transmission protrusion is provided. The substrate has a first surface and a second surface opposite to the first surface, wherein the first surface is divided into a visual region and a non-visual region. The light shielding layer is disposed in the non-visual region. The touch sensing device layer is disposed on the first surface of the substrate. The protective layer disposed on the first surface of the substrate covers the light shielding layer and the touch sensing device layer. The light transmission protrusion is disposed on the protective layer, and at least part of the light transmission protrusion is in the non-visual region. A light enters the light transmission protrusion from the second surface. A touch display device and an assembling method thereof are also provided.Type: GrantFiled: May 15, 2012Date of Patent: December 29, 2015Assignee: Au Optronics CorporationInventors: Wen-Chi Chuang, Chia-Chun Yeh, Pei-Jung Wu, Cheng-Ta Ho
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Publication number: 20150371976Abstract: A pixel structure located on a periphery of a display module includes a substrate, a flexible circuit board and a plurality of LED chips. The substrate has at least one scribing tolerance reserving zone and a display unit mounting zone. The flexible circuit board is disposed on the display unit mounting zone of the substrate. The LED chips are mounted on the flexible circuit board.Type: ApplicationFiled: June 3, 2015Publication date: December 24, 2015Inventors: Yung-Sheng CHANG, Chia-Chun YEH
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Publication number: 20150357475Abstract: A metal oxide thin film transistor (TFT) includes a gate electrode, a gate insulating layer, a metal oxide active layer, a source electrode, and a drain electrode. The gate electrode is formed on a substrate. The gate insulating layer is formed on the substrate and covers the gate electrode. The metal oxide active layer is formed on the gate insulating layer. The drain electrode and the source electrode are formed on two opposite ends of the metal oxide active layer in a spaced-apart manner, in which at least one of the orthographic projection of the source electrode and the orthographic projection of the drain electrode on the substrate does not overlap the gate electrode.Type: ApplicationFiled: August 13, 2015Publication date: December 10, 2015Inventors: Chia-Chun YEH, Henry WANG, Xue-Hung TSAI, Chih-Hsuan WANG
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Patent number: 9182641Abstract: The signal line structure is disposed between a gate driver and a display area of a display. The signal line structure includes a substrate, first metal layers, a first insulation layer, second metal layers, a second insulation layer and third metal layers. The first metal layers are arranged in parallel and toward a first direction in the substrate. The first insulation layer is disposed in the substrate and covers the first metal layers. The second metal layers are disposed on the positions of the first insulation layer corresponding to the first metal layers. The second insulation layer is disposed on the second metal layers and the first insulation layer. The third metal layers are disposed on the positions corresponding to the second metal layers in the second insulation layer. The distance between two adjacent second metal layers is less than that between two adjacent first metal layers.Type: GrantFiled: June 23, 2011Date of Patent: November 10, 2015Assignee: E Ink Holdings Inc.Inventors: Wei-Chou Lan, Sung-Hui Huang, Chia-Chun Yeh, Ted-Hong Shinn
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Patent number: 9165955Abstract: Disclosed herein is a method for manufacturing an array substrate. The method includes forming a source electrode and a drain electrode on a substrate. A semiconductor layer, an organic insulating layer, and a gate electrode layer are sequentially formed to cover the substrate, the source electrode, and the drain electrode. A patterned photoresist layer is formed on the gate electrode layer. The exposed portion of the gate electrode layer, and a portion of the organic insulative layer and a portion of the semiconductor layer thereunder are removed to form a gate electrode. An organic passivation layer is formed on the gate electrode, the source electrode, and the drain electrode. The organic passivation layer has a contact window to expose a portion of the drain electrode. A pixel electrode is formed on the organic passivation layer and the exposed portion of the drain electrode.Type: GrantFiled: June 21, 2012Date of Patent: October 20, 2015Assignee: E Ink Holdings Inc.Inventors: Wei-Chou Lan, Ted-Hong Shinn, Henry Wang, Chia-Chun Yeh
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Patent number: 9142628Abstract: A metal oxide thin film transistor (TFT) includes a gate electrode, a gate insulating layer, a metal oxide active layer, a source electrode, and a drain electrode. The gate electrode is formed on a substrate. The gate insulating layer is formed on the substrate and covers the gate electrode. The metal oxide active layer is formed on the gate insulating layer. The drain electrode and the source electrode are formed on two opposite ends of the metal oxide active layer in a spaced-apart manner, in which at least one of the orthographic projection of the source electrode and the orthographic projection of the drain electrode on the substrate does not overlap the gate electrode.Type: GrantFiled: August 22, 2012Date of Patent: September 22, 2015Assignee: E Ink Holdings Inc.Inventors: Chia-Chun Yeh, Henry Wang, Xue-Hung Tsai, Chih-Hsuan Wang
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Patent number: 9123691Abstract: Disclosed herein is a thin film transistor. The thin film transistor is characterized in having a source interconnect layer and a drain interconnect layer. The source electrode and the drain electrode are respectively disposed above and in contact with the source interconnect layer and the drain interconnect layer. The semiconductor layer is in contact with both the source interconnect layer and the drain interconnect layer, but is not in contact with the source electrode and the drain electrode.Type: GrantFiled: September 14, 2012Date of Patent: September 1, 2015Assignee: E Ink Holdings Inc.Inventors: Henry Wang, Chia-Chun Yeh, Xue-Hung Tsai, Chih-Hsuan Wang, Ted-Hong Shinn
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Patent number: 9116372Abstract: An exemplary driving substrate includes a substrate, a plurality of first and second signal transmission lines, a first insulation layer and a plurality of switch devices. The first signal transmission lines are disposed on the substrate, and each includes a first line segment(s) and a first connecting segment(s). The first insulation layer is disposed between each first line segment and each first connecting segment, and each first connecting segment is electrically connected to the adjacent first line segment(s) through an opening(s) of the first insulation layer. The second signal transmission lines are disposed on the substrate and electrically insulated and intersected with the first signal transmission lines thereby defining a plurality of pixel regions on the substrate. The switch devices are respectively disposed in the pixel regions, and each is electrically connected to corresponding first and second signal transmission lines. The driving substrate has better reliability.Type: GrantFiled: May 25, 2012Date of Patent: August 25, 2015Assignee: E INK HOLDINGS INC.Inventors: Henry Wang, Ted-Hong Shinn, Chia-Chun Yeh, Wei-Chou Lan
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Publication number: 20150233851Abstract: A semiconductor sensing device that includes a nanowire conductive layer, a semiconductor sensing layer, and a conductive layer is provided. The nanowire conductive layer includes a plurality of connected conductive nanowires, and gaps are formed between the conductive nanowires. The semiconductor sensing layer is electrically connected to the nanowire conductive layer. The conductive layer is electrically connected to the semiconductor sensing layer. The semiconductor sensing layer is located between the nanowire conductive layer and the conductive layer. A manufacturing method of a semiconductor sensing device is also provided.Type: ApplicationFiled: December 9, 2014Publication date: August 20, 2015Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Pei-Chen Yu, Ming-Yen Chuang, Chia-Chun Yeh
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Patent number: 9112042Abstract: A thin film transistor suitable for being disposed on a substrate is provided. The thin film transistor includes a gate electrode, an organic gate dielectric layer, a metal oxide semiconductor layer, a source electrode and a drain electrode. The gate electrode is disposed on the substrate. The organic gate dielectric layer is disposed on the substrate to cover the gate electrode. The source electrode, the drain electrode and the metal oxide semiconductor layer are disposed above the organic gate dielectric layer, and the metal oxide semiconductor layer contacts with the source electrode and the drain electrode. Because the channel layer of the thin film transistor is a layer of metal oxide semiconductor formed at a lower temperature, thus the thin film transistor can be widely applied into various display applications such as flexible display devices.Type: GrantFiled: September 12, 2012Date of Patent: August 18, 2015Assignee: E INK HOLDINGS INC.Inventors: Wei-Chou Lan, Ted-Hong Shinn, Henry Wang, Chia-Chun Yeh
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Patent number: 9105730Abstract: A thin film transistor and a fabrication method thereof are provided. A metal patterning layer is formed on the metal oxide semiconductor layer of a thin film transistor to shield the metal oxide semiconductor layer from the water, oxygen and light in the environment.Type: GrantFiled: November 21, 2013Date of Patent: August 11, 2015Assignee: E Ink Holdings Inc.Inventors: Wei-Tsung Chen, Ted-Hong Shinn, Chuang-Chuang Tsai, Chih-Hsiang Yang, Chia-Chun Yeh, Wen-Chung Tang