Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure includes a gate electrode separated from a substrate by a gate dielectric and a pair of source/drain regions disposed within the substrate on opposite sides of the gate electrode. A lower conductive plug is disposed through a lower inter-layer dielectric (ILD) layer and contacting a first source/drain region. A capping layer is disposed directly on the lower conductive plug. An upper inter-layer dielectric (ILD) layer is disposed over the capping layer and the lower ILD layer. An upper conductive plug is disposed through the upper ILD layer and directly on the capping layer.

Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes forming a liner-free conductive structure on a cobalt conductive structure disposed on a substrate, depositing a cobalt layer on the liner-free conductive structure and exposing the liner-free conductive structure to a heat treatment. The method further includes removing the cobalt layer from the liner-free conductive structure.

Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

Abstract: A method for forming a fin field effect transistor device structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes growing a source/drain epitaxial structure over the fin structure. The method also includes depositing a first dielectric layer surrounding the source/drain epitaxial structure. The method also includes forming a contact structure in the first dielectric layer over the source/drain epitaxial structure. The method also includes depositing a second dielectric layer over the first dielectric layer. The method also includes forming a hole in the second dielectric layer to expose the contact structure. The method also includes etching the contact structure to enlarge the hole in the contact structure. The method also includes filling the hole with a conductive material.

Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure includes a gate electrode separated from a substrate by a gate dielectric and a pair of source/drain regions disposed within the substrate on opposite sides of the gate electrode. A lower conductive plug is disposed through a lower inter-layer dielectric (ILD) layer and contacting a first source/drain region. A capping layer is disposed directly on the lower conductive plug. An upper inter-layer dielectric (ILD) layer is disposed over the capping layer and the lower ILD layer. An upper conductive plug is disposed through the upper ILD layer and directly on the capping layer.

Abstract: Low-resistance contacts improve performance of integrated circuit devices that feature epitaxial source/drain regions. The low resistance contacts can be used with transistors of various types, including planar field effect transistors (FETs), FinFETs, and gate-all-around (GAA) FETs. Low-resistance junctions are formed by removing an upper portion of the source/drain region and replacing it with an epitaxially-grown boron-doped silicon germanium (SiGe) material. Material resistivity can be tuned by varying the temperature during the epitaxy process. Electrical contact is then made at the low-resistance junctions.

Abstract: A method includes forming a device region over a substrate; forming a first dielectric layer over the device region; forming an opening in the first dielectric layer; conformally depositing a first conductive material along sidewalls and bottom surfaces of the opening; depositing a second conductive material on the first conductive material to fill the opening, wherein the second conductive material is different from the first conductive material; and performing a first thermal process to form an interface region extending from a first region of the first conductive material to a second region of the second conductive material, wherein the interface region includes a homogeneous mixture of the first conductive material and the second conductive material.

Abstract: A semiconductor device includes a gate electrode, a source/drain structure, a lower contact contacting either of the gate electrode or the source/drain structure, and an upper contact disposed in an opening formed in an interlayer dielectric (ILD) layer and in direct contact with the lower contact. The upper contact is in direct contact with the ILD layer without an interposing conductive barrier layer, and the upper contact includes ruthenium.

Abstract: An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure.

Abstract: The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a bottom metal line in a first interlayer dielectric layer, forming a second interlayer dielectric layer over the bottom metal line, exposing a top surface of the bottom metal line, increasing a total surface area of the exposed top surface of the bottom metal line, forming a conductive via over the bottom metal line, and forming a top metal line over the conductive via.

Abstract: A method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. The method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. The method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. After the annealing, the method further includes performing a chemical mechanical planarization (CMP) process to remove at least a portion of the first metal.

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and methods of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a nanostructured channel region disposed between the first and second S/D regions, a gate structure surrounding the nanostructured channel region, first and second contact structures disposed on first surfaces of the first and second S/D regions, a third contact structure disposed on a second surface of the first S/D region, and an etch stop layer disposed on a second surface of the second S/D region. The third contact structure includes a metal silicide layer, a silicide nitride layer disposed on the metal silicide layer, and a conductive layer disposed on the silicide nitride layer.

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a gate structure disposed on the fin structure, a source/drain (S/D) region disposed adjacent to the gate structure, a contact structure disposed on the S/D region, and a dipole layer disposed at an interface between the ternary compound layer and the S/D region. The contact structure includes a ternary compound layer disposed on the S/D region, a work function metal (WFM) silicide layer disposed on the ternary compound layer, and a contact plug disposed on the WFM silicide layer.

Abstract: A multi-layer interconnect structure with a self-aligning barrier structure and a method for fabricating the same is disclosed. For example, the method includes forming a via through an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and a contact structure, pre-cleaning the via with a metal halide, forming a barrier structure on the contact structure in-situ during the pre-cleaning of the via with the metal halide, and depositing a second metal in the via on top of the barrier structure.

Abstract: The present disclosure provides an interconnect structure, including a first interlayer dielectric layer, a bottom metal line including a first metal in the first interlayer dielectric layer, a conductive via including a second metal over the bottom metal line, wherein the second metal is different from the first metal, and the first metal has a first type of primary crystalline structure, and the second metal has the first type of primary crystalline structure, a total area of a bottom surface of the conductive via is greater than a total cross sectional area of the conductive via, and a top metal line over the conductive via, wherein the top metal line comprises a third metal different from the second metal.

Abstract: The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.

Abstract: A semiconductor device structure according to the present disclosure includes a source feature and a drain feature, at least one channel structure extending between the source feature and the drain feature, a gate structure wrapped around each of the at least on channel structure, a semiconductor layer over the gate structure, a dielectric layer over the semiconductor layer, a doped semiconductor feature extending through the semiconductor layer and the dielectric layer to be in contact with the source feature, a metal contact plug over the doped semiconductor feature, and a buried power rail disposed over the metal contact plug.

Abstract: The present disclosure provides an interconnect structure, including a first interlayer dielectric layer, a bottom metal line including a first metal in the first interlayer dielectric layer, a conductive via including a second metal over the bottom metal line, wherein the second metal is different from the first metal, and the first metal has a first type of primary crystalline structure, and the second metal has the first type of primary crystalline structure, a total area of a bottom surface of the conductive via is greater than a total cross sectional area of the conductive via, and a top metal line over the conductive via, wherein the top metal line comprises a third metal different from the second metal.