Patents by Inventor Chia-Jen Chen

Chia-Jen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for forming fin field effect transistor (FinFET) device structure
    Patent number: 10276449
    Abstract: A method for forming a semiconductor device structure includes providing a substrate having a first fin structure and a second fin structure that are capped by a patterned hard mask structure. A liner layer and an overlying insulating layer are formed between the first and second fin structures. A multi-step etching process including a first step of selectively removing the patterned hard mask structure and a second step of in-situ and selectively removing a portion of the insulating layer to form an isolation feature is performed. The process gas used in the multi-step etching process includes a first etching gas and a second etching gas. The flow rate of the first etching gas is greater than that of the second etching gas in the first step and the flow rate of the first etching gas is less than that of the second etching gas in the second step.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Shu Wu, Ying-Ya Hsu, Shu-Uei Jang, Yu-Wen Wang, Ryan Chia-Jen Chen, An-Chyi Wei
  • Metal gate structure cutting process
    Patent number: 10269787
    Abstract: Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shiang-Bau Wang, Ming-Ching Chang, Shu-Yuan Ku, Ryan Chia-Jen Chen
  • Metal Gate Structure Cutting Process
    Publication number: 20190109126
    Abstract: Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure.
    Type: Application
    Filed: November 29, 2018
    Publication date: April 11, 2019
    Inventors: Shiang-Bau Wang, Ryan Chia-Jen Chen, Shu-Yuan Ku, Ming-Ching Chang
  • Semiconductor Device and Method
    Publication number: 20190088499
    Abstract: A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.
    Type: Application
    Filed: November 2, 2018
    Publication date: March 21, 2019
    Inventors: Ming-Jie Huang, Syun-Ming Jang, Ryan Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Tai-Chun Huang, Chunyao Wang, Tze-Liang Lee, Chi On Chui
  • Cut Metal Gate with Slanted Sidewalls
    Publication number: 20190088650
    Abstract: A method includes providing a structure having a substrate, semiconductor fins, and an isolation structure between adjacent semiconductor fins; forming a first gate structure engaging the semiconductor fins; depositing an inter-layer dielectric layer over the semiconductor fins and the first gate structure; removing the first gate structure, resulting in a first trench; depositing a second gate structure into the first trench, wherein the second gate structure includes a dielectric layer and a conductive layer; forming one or more mask layers over the second gate structure; patterning the one or more mask layers to have an opening exposing a portion of the second gate structure between two adjacent semiconductor fins; and etching the second gate structure through the opening to produce a second trench having tapered sidewalls, wherein the second trench is wider at top than at bottom.
    Type: Application
    Filed: November 19, 2018
    Publication date: March 21, 2019
    Inventors: Ya-Yi Tsai, Chun-Liang Lai, Shu-Yuan Ku, Ryan Chia-Jen Chen, Ming-Ching Chang
  • Cut Metal Gate with Slanted Sidewalls
    Publication number: 20190067277
    Abstract: A semiconductor device includes a substrate, first and second fins protruding out of the substrate, and first and second high-k metal gates (HK MG) disposed over the first and second fins, respectively. From a top view, the first and second fins are arranged lengthwise along a first direction, the first and second HK MG are arranged lengthwise along a second direction generally perpendicular to the first direction, and the first and second HK MG are aligned along the second direction. In a cross-sectional view cut along the second direction, the first HK MG has a first sidewall that is slanted from top to bottom towards the second HK MG, and the second HK MG has a second sidewall that is slanted from top to bottom towards the first HK MG. Methods for producing the semiconductor device are also disclosed.
    Type: Application
    Filed: February 26, 2018
    Publication date: February 28, 2019
    Inventors: Ya-Yi Tsai, Chun-Liang Lai, Shu-Yuan Ku, Ryan Chia-Jen Chen, Ming-Ching Chang
  • FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20190043857
    Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a first fin structure extending above a substrate, and the first fin structure includes a portion made of silicon germanium (SiGe). The FinFET device structure includes a second fin structure adjacent to the first fin structure. The FinFET device structure also includes a first liner layer formed on the outer sidewall surface of the first fin structure and a second liner layer formed on the inner sidewall surface of the first fin structure. The FinFET device structure further includes a first isolation structure formed on the substrate, and the first liner layer is between the first isolation structure and the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer.
    Type: Application
    Filed: August 4, 2017
    Publication date: February 7, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Shu WU, Shu-Uei JANG, Wei-Yeh TANG, Ryan Chia-Jen CHEN, An-Chyi WEI
  • Metal gate isolation structure and method forming same
    Patent number: 10186511
    Abstract: A device includes a gate isolation plug, which further includes a U-shaped layer having a bottom portion and two sidewall portions, and an inner region overlapping the bottom portion. The inner region contacts the two sidewall portions. A first transistor has a first gate stack, and a first end of the first gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. A second transistor has a second gate stack, and a second end of the second gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. The first gate stack and the second gate stack are on opposite sides of the gate isolation plug.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: January 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Han Lin, Wen-Shuo Hsieh, Ming-Jie Huang, Ryan Chia-Jen Chen
  • METAL GATE STRUCTURE CUTTING PROCESS
    Publication number: 20190006345
    Abstract: Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure.
    Type: Application
    Filed: November 10, 2017
    Publication date: January 3, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: SHIANG-BAU WANG, MING-CHING CHANG, SHU-YUAN KU, RYAN CHIA-JEN CHEN
  • PHOTOMASK INCLUDING FIDUCIAL MARK, METHOD OF PATTERNING THE PHOTOMASK AND METHOD OF MAKING SEMICONDUCTOR DEVICE USING THE PHOTOMASK
    Publication number: 20180364560
    Abstract: A photomask includes a pattern region and a plurality of defects in the pattern region. The photomask further includes a first fiducial mark outside of the pattern region, wherein the first fiducial mark includes identifying information for the photomask, the first fiducial mark has a first size and a first shape. The photomask further includes a second fiducial mark outside of the pattern region. The second fiducial mark has a second size different from the first size, or a second shape different from the first shape.
    Type: Application
    Filed: June 19, 2017
    Publication date: December 20, 2018
    Inventors: Hsin-Chang LEE, Chia-Jen CHEN, Chih-Cheng LIN, Ping-Hsun LIN
  • Semiconductor device and method
    Patent number: 10134604
    Abstract: A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Jie Huang, Syun-Ming Jang, Ryan Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Tai-Chun Huang, Chunyao Wang, Tze-Liang Lee, Chi On Chui
  • Methods for Forming Fin Field-Effect Transistors
    Publication number: 20180323108
    Abstract: A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.
    Type: Application
    Filed: June 29, 2018
    Publication date: November 8, 2018
    Inventors: Ryan Chia-Jen Chen, Yih-Ann Lin, Chia Tai Lin, Chao-Cheng Chen
  • SEMICONDUCTOR DEVICE AND METHOD
    Publication number: 20180315618
    Abstract: A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.
    Type: Application
    Filed: October 5, 2017
    Publication date: November 1, 2018
    Inventors: Ming-Jie Huang, Syun-Ming Jang, Ryan Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Tai-Chun Huang, Chunyao Wang, Tze-Liang Lee, Chi On Chui
  • GATE STRUCTURE OF A SEMICONDUCTOR DEVICE
    Publication number: 20180277654
    Abstract: A CMOS semiconductor device includes a substrate comprising an isolation region separating a P-active region and an N-active region. The CMOS semiconductor device further includes a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode includes a P-work function metal and a doped TiN layer between the P-work function metal and substrate. The CMOS semiconductor device further includes an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode includes an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein a portion of the P-metal gate electrode is between a portion of the N-metal gate electrode and the substrate.
    Type: Application
    Filed: May 21, 2018
    Publication date: September 27, 2018
    Inventors: Ming ZHU, Hui-Wen LIN, Harry Hak-Lay CHUANG, Bao-Ru YOUNG, Yuan-Sheng HUANG, Ryan Chia-Jen CHEN, Chao-Cheng CHEN, Kuo-Cheng CHING, Ting-Hua HSIEH, Carlos H. DIAZ
  • Methods for forming Fin field-effect transistors
    Patent number: 10083872
    Abstract: A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: September 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ryan Chia-Jen Chen, Yih-Ann Lin, Chia Tai Lin, Chao-Cheng Chen
  • Method of Forming a Single Metal that Performs N Work Function and P Work Function in a High-K/Metal Gate Process
    Publication number: 20180247937
    Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure in the semiconductor substrate for isolating a first active region and a second active region, a first device formed in the first active region, and a second device formed in the second active region. The first device has a first gate dielectric layer and a first gate electrode over the first gate dielectric layer. The first gate electrode includes at least one of Ta and C, and has a first work function for a first conductivity. The second device has a second gate dielectric layer and a second gate electrode over the second gate dielectric layer. The second gate electrode includes at least one of Ta, C, and Al, and has a second work function for a second conductivity. The second conductivity is different from the first conductivity.
    Type: Application
    Filed: April 25, 2018
    Publication date: August 30, 2018
    Inventors: Yih-Ann Lin, Ryan Chia-Jen Chen, Donald Y. Chao, Yi-Shien Mor, Kuo-Tai Huang
  • Metal Gate Isolation Structure and Method Forming Same
    Publication number: 20180204836
    Abstract: A device includes a gate isolation plug, which further includes a U-shaped layer having a bottom portion and two sidewall portions, and an inner region overlapping the bottom portion. The inner region contacts the two sidewall portions. A first transistor has a first gate stack, and a first end of the first gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. A second transistor has a second gate stack, and a second end of the second gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. The first gate stack and the second gate stack are on opposite sides of the gate isolation plug.
    Type: Application
    Filed: March 12, 2018
    Publication date: July 19, 2018
    Inventors: Chih-Han Lin, Wen-Shuo Hsieh, Ming-Jie Huang, Ryan Chia-Jen Chen
  • Lithography mask
    Patent number: 9995999
    Abstract: A lithography mask includes a substrate, a reflective multilayer (ML) on the substrate, and a barrier layer on the reflective ML. The barrier layer includes at least one material selected from the group consisting of ruthenium nitride, hafnium oxide, aluminum nitride, boron carbide, boron nitride, and a combination thereof.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yun-Yue Lin, Hsin-Chang Lee, Chia-Jen Chen, Anthony Yen
  • LITHOGRAPHY MASK WITH BOTH TRANSMISSION-TYPE AND REFLECTIVE-TYPE OVERLAY MARKS AND METHOD OF FABRICATING THE SAME
    Publication number: 20180149959
    Abstract: A lithography mask includes a substrate that contains a low thermal expansion material (LTEM). A reflective structure is disposed over a first side of the substrate. An absorber layer is disposed over the reflective structure. The absorber layer contains one or more first overlay marks. A conductive layer is disposed over a second side of the substrate, the second side being opposite the first side. The conductive layer contains portions of one or more second overlay marks. In some embodiments, the lithography mask includes an EUV lithography mask.
    Type: Application
    Filed: August 7, 2017
    Publication date: May 31, 2018
    Inventors: Yun-Yue Lin, Hsin-Chang Lee, Chia-Jen Chen, Chih-Cheng Lin, Anthony Yen, Chin-Hsiang Lin
  • Method of forming gate structure of a semiconductor device
    Patent number: 9978853
    Abstract: A method of fabricating a semiconductor device includes forming a gate strip including a dummy electrode and a TiN layer. The method includes removing a first portion of the dummy electrode to form a first opening over a P-active region and an isolation region. The method includes performing an oxygen-containing plasma treatment on a first portion of the TiN layer; and filling the first opening with a first metal material. The method includes removing a second portion of the dummy electrode to form a second opening over an N-active region and the isolation region. The method includes performing a nitrogen-containing plasma treatment on a second portion of the TiN layer; and filling the second opening with a second metal material. The second portion of the TiN layer connects to the first portion of the TiN layer over the isolation region.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: May 22, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming Zhu, Hui-Wen Lin, Harry Hak-Lay Chuang, Bao-Ru Young, Yuan-Sheng Huang, Ryan Chia-Jen Chen, Chao-Cheng Chen, Kuo-Cheng Ching, Ting-Hua Hsieh, Carlos H. Diaz