Patents by Inventor Chia LING

Chia LING has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240162602
    Abstract: An electronic device is provided. The electronic device includes a first substrate, an insulating layer, a first conductive layer and a second conductive layer. The insulating layer is overlapped with the first substrate. The second conductive layer contacts with the first conductive layer. The first conductive layer and the second conductive layer are disposed between the first substrate and the insulating layer. The second conductive layer is disposed between the first conductive layer and the insulating layer. Moreover, a thermal expansion coefficient of the second conductive layer is between a thermal expansion coefficient of the first conductive layer and a thermal expansion coefficient of the insulating layer.
    Type: Application
    Filed: January 2, 2024
    Publication date: May 16, 2024
    Inventors: Chia-Ping TSENG, Ker-Yih KAO, Chia-Chi HO, Ming-Yen WENG, Hung-I TSENG, Shu-Ling WU, Huei-Ying CHEN
  • Publication number: 20240153788
    Abstract: An addition system of a reducing agent in a semiconductor manufacturing process includes pre-treatment and post-treatment gas concentration detection devices, a process exhaust gas treatment device, a reducing agent supply device, and an addition system control device. The process exhaust gas treatment device purifies exhaust gas of a semiconductor manufacturing process and emits a post-treatment gas. The reducing agent supply device supplies a reducing agent gas into the process exhaust gas treatment device. The post-treatment gas concentration detection device detects a residual concentration of the reducing agent gas in the post-treatment gas. The addition system control device calculates destruction and removal efficiency (DRE) for process gases according to pre-treatment and post-treatment gas concentrations, and, according to the DRE and the residual concentration, sends a signal to the reducing agent supply device to control the amount of the reducing agent gas added.
    Type: Application
    Filed: July 27, 2023
    Publication date: May 9, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Jia-Cheng Sun, Jui-Hsiang Cheng, I-Ling Nien, Chia-Yen Kuo, Shou-Nan Li
  • Publication number: 20240142961
    Abstract: A method of estimating greenhouse gas emission, performed by a processing device, includes: obtaining at least one time period of a number of working stations for a target manufacturing process of a product; obtaining a number of first power consumption data of the target manufacturing process, wherein the first power consumption data correspond to the working stations respectively; calculating a number of second power consumption data based on the at least one time period and the first power consumption data; searching for a number of target coefficients corresponding to the plurality of working stations respectively in coefficient database based on the target manufacturing process; and calculating greenhouse gas emission data of the target manufacturing process based on the second power consumption data and the target coefficients.
    Type: Application
    Filed: October 27, 2022
    Publication date: May 2, 2024
    Applicant: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Tsung-Hsi LIN, Yun Sheng LI, Yu Ling LEE, Hsiao Pin LIN, Chia Hou CHEN
  • Patent number: 11974506
    Abstract: A spin-orbit torque device is disclosed, which includes: a magnetic layer; and a non-magnetic layer adjacent to the magnetic layer and comprising a spin-Hall material, wherein the spin-Hall material comprises NixCu1-x alloy, and x is in a range from 0.4 to 0.8.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: April 30, 2024
    Assignees: NATIONAL TAIWAN UNIVERSITY, ACADEMIA SINICA
    Inventors: Po-Hsun Wu, Ssu-Yen Huang, Chia-Ling Chien, Danru Qu
  • Publication number: 20240134268
    Abstract: A mask for use in a semiconductor lithography process includes a substrate, a mask pattern disposed on the substrate, and a light absorbing border surrounding the mask pattern. The light absorbing border is inset from at least two edges of the substrate to define a peripheral region outside of the light absorbing border. In some designs, a first peripheral region extends from an outer perimeter of the light absorbing border to a first edge of the substrate, and a second peripheral region that extends from the outer perimeter of the light absorbing border to a second edge of the substrate, where the first edge of the substrate and the second edge of the substrate are on opposite sides of the mask pattern.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Inventors: Chien-Cheng Chen, Huan-Ling Lee, Ta-Cheng Lien, Chia-Jen Chen, Hsin-Chang Lee
  • Publication number: 20240136291
    Abstract: Semiconductor devices and methods of forming the same are provided. In some embodiments, a method includes receiving a workpiece having a redistribution layer disposed over and electrically coupled to an interconnect structure. In some embodiments, the method further includes patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, where corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess. The method further includes depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess. The method further includes depositing a nitride layer over the first dielectric layer. In some examples, the method further includes removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.
    Type: Application
    Filed: January 12, 2023
    Publication date: April 25, 2024
    Inventors: Hsiang-Ku SHEN, Chen-Chiu HUANG, Chia-Nan LIN, Man-Yun WU, Wen-Tzu CHEN, Sean YANG, Dian-Hao CHEN, Chi-Hao CHANG, Ching-Wei LIN, Wen-Ling CHANG
  • Patent number: 11964299
    Abstract: A method for manufacturing a golf ball having a multi-layered pattern is provided. Firstly, a semi-finished product of the golf ball is provided and includes a ball-shaped body and a base layer covering an outer surface of the ball-shaped body. Then, the semi-finished product of the golf ball is rotated at a predetermined rotation speed, and a color paint is applied to the semi-finished product of the golf ball by spraying from each of an upper position, a middle position, and a lower position. The multi-layered pattern includes an upper-layer pattern area, a mid-layer pattern area, and a lower-layer pattern area that are different in color from each other.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: April 23, 2024
    Assignee: FOREMOST GOLF MFG. LTD.
    Inventors: Chia-Sheng Huang, Chi-Ling Lin, Chia-Cheng Wu, Ching-Hsiang Liu
  • Publication number: 20240128404
    Abstract: A light-emitting diode includes a first type semiconductor layer, a stress relief layer disposed on the first type semiconductor layer and including at least one first repeating unit containing a first well layer and a first barrier layer that are alternately stacked, an active layer disposed on the stress relief layer and including at least one second repeating unit containing a second well layer and a second barrier layer that are alternately stacked, a second type semiconductor layer disposed on the active layer, a first electrode electrically connected to the first type semiconductor layer, and a second electrode electrically connected to the second type semiconductor layer. The first well layer is made of an In-containing material. The second well layer is made of an In-containing material. The second barrier layer is formed with multiple sub-layers, each of which is made of an Al-containing material.
    Type: Application
    Filed: December 20, 2023
    Publication date: April 18, 2024
    Inventors: Yung-Ling LAN, Chenghung LEE, Chan-Chan LING, Chia-Hao CHANG
  • Publication number: 20240124844
    Abstract: The present disclosure provides a method for preparing a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors, the composition prepared by the method, and use of the composition for treating arthritis. The composition of the present disclosure achieves the effect of treating arthritis through various efficacy experiments.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 18, 2024
    Inventors: Chia-Hsin Lee, Po-Cheng Lin, Yong-Cheng Kao, Ming-Hsi Chuang, Chun-Hung Chen, Chao-Liang Chang, Kai-Ling Zhang
  • Publication number: 20240128125
    Abstract: A method of forming a semiconductor device includes providing a substrate having a recess, and growing an epitaxial feature in the recess. The method of growing the epitaxial feature includes: (a) growing a sub-layer of the epitaxial feature; (b) selectively etching the sub-layer of the epitaxial feature while providing a first UV radiation; and (c) repeating step (a) and step (b) alternately multiple times.
    Type: Application
    Filed: February 1, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Winnie Victoria Wei-Ning Chen, Chia-Ling Pai, Pang-Yen Tsai
  • Publication number: 20240117314
    Abstract: The present invention relates to a method for preparing a modified stem cell, including the following steps: a cell culture step: culturing stem cells in a first culture medium of a culture dish at a predetermined cell density, and removing the first culture medium after a first culture time to obtain a first cell intermediate; an activity stimulation step: preserving the first cell intermediate in a freezing container having a cell cryopreservation solution, and performing a constant temperature stimulation treatment or a variable temperature stimulation treatment for at least more than 1 day; and a product collection step: after completing the activity stimulation step, placing the freezing container in an environment at a thawing temperature for thawing, and then removing the cell cryopreservation solution to obtain the modified stem cell. The modified stem cell can release at least one or more of IL-4, IL-5, IL-13, G-CSF, Fractalkine, and EGF.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 11, 2024
    Inventors: Ruei-Yue Liang, Chia-Hsin Lee, Kai-Ling Zhang, Po-Cheng Lin, Ming-Hsi Chuang, Yu-Chen Tsai, Peggy Leh Jiunn Wong
  • Publication number: 20240120325
    Abstract: A stacked package structure and a manufacturing method thereof are provided. The stacked package structure includes an upper redistribution layer, a first chip, and an upper molding layer. The first chip is disposed on the upper redistribution layer and is electrically connected to the upper redistribution layer. The upper molding layer is disposed on the first chip and the upper redistribution layer, and is configured to package the first chip. The upper molding layer includes a recess, the recess is recessed relative to a surface of the upper molding layer away from the upper redistribution layer, and the recess is circumferentially formed around a periphery of the upper molding layer.
    Type: Application
    Filed: May 31, 2023
    Publication date: April 11, 2024
    Applicant: POWERTECH TECHNOLOGY INC.
    Inventors: Pei-chun TSAI, Hung-hsin HSU, Shang-yu CHANG CHIEN, Chia-ling LEE
  • Publication number: 20240120437
    Abstract: A manufacturing method for a LED is disclosed. The method includes: providing a substrate with an upper surface; preparing a plurality of LEDs on the upper surface; wherein the upper surface is divided into a plurality of zones, the plurality of LEDs composes a plurality of LED groups, and each of the LED group is disposed in one of the plurality of zones; preparing a testing circuit to electrically connecting the plurality of LEDs in one of the plurality of LED groups; testing the plurality of LEDs in the one of the plurality of LED groups by the testing circuit to obtain photoelectrical characteristics of the plurality of LEDs in the one of the plurality of LED groups; and presenting the photoelectric characteristics in an image.
    Type: Application
    Filed: December 11, 2023
    Publication date: April 11, 2024
    Inventors: Chia-Chen TSAI, Jia-Liang TU, Chi-Ling LEE
  • Publication number: 20240115616
    Abstract: The present disclosure provides a method for treating liver cirrhosis by using a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors. The composition of the present disclosure achieves the effect of treating liver cirrhosis through various efficacy experiments.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 11, 2024
    Inventors: Po-Cheng Lin, Pi-Chun Huang, Zih-Han Hong, Ming-Hsi Chuang, Yi-Chun Lin, Chia-Hsin Lee, Chun-Hung Chen, Chao-Liang Chang, Kai-Ling Zhang
  • Publication number: 20240113254
    Abstract: A semiconductor light emitting device includes a multi-quantum-well structure, a first capping layer, a second capping layer, and an electron barrier layer stacked in order. The multi-quantum-well structure includes a plurality of alternately-stacked potential barrier layers and potential well layers. The first capping layer is a semiconductor layer, and the second capping layer is a p-doped semiconductor layer. Each of the first and second capping layers has an aluminum mole fraction larger than that of each of the potential barrier layers, and the aluminum mole fraction of the first capping layer is larger than that of at least a portion of the electron barrier layer. A method for preparing the semiconductor light emitting device is also provided.
    Type: Application
    Filed: December 15, 2023
    Publication date: April 4, 2024
    Inventors: Yung-Ling LAN, Chan-Chan LING, Chi-Ming TSAI, Chia-Hung CHANG
  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Patent number: 11931187
    Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: March 19, 2024
    Assignees: Chang Gung Medical Foundation Chang Gung Memorial Hospital at Keelung, Chang Gung Memorial Hospital, Linkou, Chang Gung University
    Inventors: Jiun-Jie Wang, Yi-Hsin Weng, Shu-Hang Ng, Jur-Shan Cheng, Yi-Ming Wu, Yao-Liang Chen, Wey-Yil Lin, Chin-Song Lu, Wen-Chuin Hsu, Chia-Ling Chen, Yi-Chun Chen, Sung-Han Lin, Chih-Chien Tsai
  • Publication number: 20240088246
    Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Yu-Ling Hsu, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Wen-Tuo Huang, Yong-Shiuan Tsair, Chia-Sheng Lin, Shih Kuang Yang
  • Publication number: 20240088284
    Abstract: Disclosed is a semiconductor device and a method for fabricating such semiconductor device, specifically a High Electron Mobility Transistor (HEMT) with a back barrier layer for blocking electron leakage and improve threshold voltage. In one embodiment, a semiconductor device, includes: a Gallium Nitride (GaN) layer; a front barrier layer over the GaN layer; a source electrode, a drain electrode and a gate electrode formed over the front barrier layer; a 2-Dimensional Electron Gas (2-DEG) in the GaN layer at a first interface between the GaN layer and the front barrier layer; and a back barrier layer in the GaN layer, wherein the back barrier layer comprises Aluminum Nitride (AlN).
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Inventors: Chia-Ling YEH, Pravanshu MOHANTA, Ching-Yu CHEN, Jiang-He XIE, Yu-Shine LIN
  • Patent number: 11927488
    Abstract: A thermal detection system is provided. The thermal detection system includes a thermal detector, an area indicating unit and a control unit. The thermal detector includes a thermal sensor array. The thermal detector is configured to detect thermal radiation within a detection area around the thermal detector. The detection area is defined by a field of view of the thermal sensor array. The area indicating unit is arranged to indicate a human-perceptible area according to the detection area. The human-perceptible area is located within the detection area and indicates a geometric form of the detection area. The control unit, coupled to the thermal detector and the area indicating unit, is configured to generate a thermal detection result according to the detected thermal radiation. The thermal detection system further includes a notification unit for overheat indication, a communication unit for wireless signal transmission, and a protection unit for overheat protection.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: March 12, 2024
    Inventor: Chia-Ling Chen