Abstract: A method of fabricating a semiconductor device is described. A substrate is provided. A first semiconductor region of a first semiconductor material is formed over the substrate and adjacent a second semiconductor region of a second semiconductor material. The first and second semiconductor regions are crystalline. An etchant is selective to etch the first semiconductor region over the second semiconductor region. The entire first semiconductor region is implanted to form an amorphized semiconductor region. The amorphized semiconductor region is etched with the etchant using the second semiconductor region as a mask to remove the amorphized semiconductor region without removing the second semiconductor region.

Abstract: Disclosed is a semiconductor device and a method for fabricating such semiconductor device, specifically a High Electron Mobility Transistor (HEMT) with a back barrier layer for blocking electron leakage and improve threshold voltage. In one embodiment, a semiconductor device, includes: a Gallium Nitride (GaN) layer; a front barrier layer over the GaN layer; a source electrode, a drain electrode and a gate electrode formed over the front barrier layer; a 2-Dimensional Electron Gas (2-DEG) in the GaN layer at a first interface between the GaN layer and the front barrier layer; and a back barrier layer in the GaN layer, wherein the back barrier layer comprises Aluminum Nitride (AlN).

Abstract: An endoscope decontamination sheath includes a terminal section for seeing therethrough for an image and a sleeve section connected to the terminal section for receiving an endoscope to insert therein. The terminal section is of a tubular configuration. The terminal section has a front end to which a lens is mounted and a rear end in which an insertion groove is formed. The sleeve section is of an elongated tubular configuration having a front end fit into the insertion groove of the terminal section. In medical treatment of endoscopy or intubation, the endoscope is inserted into and sleeved with the sleeve section, and the endoscope sleeved with the decontamination sheath is inserted into an endotracheal tube. The matched arrangement between the lens and a lens of the endoscope helps prevent image deterioration and thus making images clearer. The decontamination sheath, after use, can be disposed of to prevent cross infection.

Abstract: A method of cleaning wafer-cleaning brushes includes passing a wafer having a first polished main side and an opposing unpolished backside between a pair of substantially cylindrical shaped wafer-cleaning brushes are rotated about an axial direction of the brushes while passing the wafer between the pair of wafer-cleaning brushes. A cleaning solution is applied to the brushes while passing the wafer between the pair of wafer-cleaning brushes. While passing between the pair of brushes, the first polished main side of the wafer faces a first direction, the first direction is an opposite direction to which a polished side of a production wafer faces during a subsequent polished wafer cleaning operation. The substantially cylindrical shaped wafer-cleaning brushes include a plurality of protrusions on an external surface of the brushes, and the brushes contact the wafer at least a portion of time the wafer is passing between the pair of brushes.

Abstract: A disclosed semiconductor structure may include an interposer, a first semiconductor die electrically coupled to the interposer, a packaging substrate electrically coupled to the interposer, and a capping layer covering one or more of a first surface of the first semiconductor die and a second surface of the packaging substrate. The capping layer may be formed over respective surfaces of each of the first semiconductor die and the packaging substrate. In certain embodiments, the capping layer may be formed only on the first surface of the first semiconductor die and not formed over the package substrate. In further embodiments, the semiconductor structure may include a second semiconductor die, such that the capping layer covers a surface of only one of the first semiconductor die and the second semiconductor die. The semiconductor structure may include a molding compound die frame that is partially or completely covered by the capping layer.

Abstract: Strain relief trenches may be formed in a substrate prior to growth of an epitaxial layer on the substrate. The trenches may reduce the stresses and strains on the epitaxial layer that occur during the epitaxial growth process due to differences in material properties (e.g., lattice mismatches, differences in thermal expansion coefficients, and/or the like) between the epitaxial layer material and the substrate material. The stress and strain relief provided by the trenches may reduce or eliminate cracks and/or other types of defects in the epitaxial layer and the substrate, may reduce and/or eliminate bowing and warping of the substrate, may reduce breakage of the substrate, and/or the like. This may increase the center-to-edge quality of the epitaxial layer, may permit epitaxial layers to be grown on larger substrates, and/or the like.

Abstract: A method for selectively removing a tungsten-including layer includes: forming a tungsten-including layer which has a first portion and a second portion; performing a treatment on a surface region of the first portion of the tungsten-including layer so as to convert tungsten in the surface region into tungsten oxide; and partially removing the tungsten-including layer using an etchant which has a higher etching selectivity to tungsten than tungsten oxide such that the second portion of the tungsten-including layer is fully removed, and the first portion of the tungsten-including layer, having the tungsten oxide in the surface region, is at least partially retained.

Abstract: An integrated vapor chamber includes an outer shell and a plurality of composite capillary structures. The outer shell includes a flat casing and a plurality of partitions integrally formed. The flat shell includes a chamber, and the partitions are disposed in the chamber to separate the chamber into a plurality of flow channels. Each composite capillary structure is extended along each flow channel and distributed in the chamber. The composite capillary structure includes a metal mesh and a plurality of sintered powder uniformly sintered in the metal mesh. Furthermore, this disclosure also discloses a manufacturing method of the integrated vapor chamber. Therefore, the manufacturing method of the thin vapor chamber is simplified to improve the yield rate.

Abstract: Strain relief trenches may be formed in a substrate prior to growth of an epitaxial layer on the substrate. The trenches may reduce the stresses and strains on the epitaxial layer that occur during the epitaxial growth process due to differences in material properties (e.g., lattice mismatches, differences in thermal expansion coefficients, and/or the like) between the epitaxial layer material and the substrate material. The stress and strain relief provided by the trenches may reduce or eliminate cracks and/or other types of defects in the epitaxial layer and the substrate, may reduce and/or eliminate bowing and warping of the substrate, may reduce breakage of the substrate, and/or the like. This may increase the center-to-edge quality of the epitaxial layer, may permit epitaxial layers to be grown on larger substrates, and/or the like.

Abstract: Techniques for managing an engagement zone include tracking, by a system, a hand of a user and determining that a height of the hand of the user satisfies a first threshold height. In accordance with determining that the height of the hand of the user satisfies the first threshold height, the techniques also include initiating a UI engagement state, wherein the system monitors the user for user input during the UI engagement state, and determining user input into the system based on a user motion detected while the hand is tracked. The threshold height is associated with a boundary of a UI engagement zone and is modifiable based on user activity.

Abstract: A delta-sigma modulator is provided. The delta-sigma modulator includes a multiplexer, a modulation circuit and a demultiplexer. The multiplexer is configured to receive a first analog signal and a second analog signal, and output an input signal. The first analog signal and the second analog signal are in different electrical forms, and the multiplexer is configured to select, in a time-division manner, the first analog signal or the second analog signal as the input signal SIN to be output. The modulation circuit is configured to modulate the input signal into a digital signal. The demultiplexer has a first output terminal and a second output terminal, and selects the first output terminal or the second output terminal in a time-division manner to output the digital signal.

Abstract: A signal processing circuit includes an input buffer circuit and a direct-(DC) voltage detector circuit. The input buffer circuit is coupled to a pin. The pin is configured to receive an input signal. The DC voltage detector circuit is coupled to the pin and the input buffer circuit. The DC voltage detector circuit is configured to detect the input signal to generate a mode signal and generate a bias of the input buffer circuit according to the mode signal.

Abstract: Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first recess and a second recess are formed in a first region and a second region of a semiconductor substrate, respectively. A bottom surface of the first recess is lower than a bottom surface of the second recess in a vertical direction. A first gate oxide layer and a second gate oxide layer are formed concurrently. At least a portion of the first gate oxide layer is formed in the first recess, and at least a portion of the second gate oxide layer is formed in the second recess. A removing process is performed for removing a part of the second gate oxide layer. A thickness of the second gate oxide layer is less than a thickness of the first gate oxide layer after the removing process.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure over a substrate. The semiconductor structure also includes a gate spacer on a sidewall of the gate structure. The semiconductor structure also includes a source/drain feature adjacent to the gate structure. The semiconductor structure also includes a doped region extending along a bottom surface of the gate spacer. The source/drain feature has a curved sidewall connecting a top surface of the doped region and a bottom surface of the doped region.

Abstract: Aspects of the present disclosure provide methods, apparatuses, and systems for closed-loop sleep protection and/or sleep regulation. According to an aspect, sleep disturbing noises are predicted and a biosignal parameter is measured to dynamically mask predicted disturbing environmental noises in the sleeping environment with active attenuation. Environmental noises in a sleeping environment of a subject are detected, input, or predicted based on historical data of the sleeping environment collected over a period of time. The biosignal parameter is used to determine sleep physiology of a subject. Based on the environmental noises in the sleeping environment and the determined sleep physiology, the noises are predicted to be disturbing or non-disturbing noises. For predicted disturbing noises, one or more actions are taken to regulate sleep and avoid sleep disruption by using sound masking prior to or concurrently with the occurrence of the predicted disturbing noises.

Abstract: An integrated vapor chamber includes an outer shell and a plurality of composite capillary structures. The outer shell includes a flat casing and a plurality of partitions integrally formed. The flat shell includes a chamber, and the partitions are disposed in the chamber to separate the chamber into a plurality of flow channels. Each composite capillary structure is extended along each flow channel and distributed in the chamber. The composite capillary structure includes a metal mesh and a plurality of sintered powder uniformly sintered in the metal mesh. Furthermore, this disclosure also discloses a manufacturing method of the integrated vapor chamber. Therefore, the manufacturing method of the thin vapor chamber is simplified to improve the yield rate.

Abstract: Semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor, a second transistor, a third transistor, and a plurality of shallow trench isolations. The first transistor is disposed in a medium-voltage region and includes a first plane, a first gate dielectric layer, and a first gate electrode. The second transistor is disposed in a boundary region and includes a second plane, a second gate dielectric layer, and a second gate electrode. The third transistor is disposed in a lower-voltage region and includes a third plane, a third gate dielectric layer, and a third gate electrode. The shallow trench isolations are disposed in the substrate, wherein top surfaces of the shallow trench isolations in the medium-voltage region, the boundary region and the low-voltage region are coplanar with top surfaces of the first gate dielectric layer and the second gate dielectric layer.

Abstract: The present invention provides a circuitry applied to multiple power domains. An amplifier of the circuitry includes an output stage and a switching circuit. The output stage includes a first transistor and a second transistor, wherein the first transistor is coupled between a supply voltage and an output terminal, the second transistor is coupled between the output terminal and a ground voltage. The switching circuit is configured to choose a body of the first transistor from the supply voltage or a reference voltage.

Abstract: A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A trench isolation structure is disposed in the substrate between the first device region and the second device region. The trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is coplanar with the second bottom surface.