Patents by Inventor Chia-Ming Tsai

Chia-Ming Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11665639
    Abstract: A method for a user equipment (UE) monitoring a physical downlink control channel (PDCCH) for power saving signaling is disclosed. The method comprises receiving a discontinuous reception (DRX) configuration from a base station (BS) to configure the UE to monitor a scheduling signal on the PDCCH within a DRX active time, and receiving a configuration from the BS to configure the UE to monitor the power saving signaling on the PDCCH and instructing the UE to wake up for monitoring the scheduling signal in the DRX active time, wherein the configuration includes a time in milliseconds prior to a start of a DRX on-duration time, and instructs the UE to start monitoring the PDCCH for the power saving signaling.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: May 30, 2023
    Assignee: Hannibal IP LLC
    Inventors: Yu-Hsin Cheng, Hsin-Hsi Tsai, Chia-Hao Yu, Chie-Ming Chou
  • Patent number: 11658224
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a source/drain region arranged within a substrate. A first select gate is arranged over the substrate, and a first memory gate is arranged over the substrate and separated from the source/drain region by the first select gate. An inter-gate dielectric structure is arranged between the first memory gate and the first select gate. The inter-gate dielectric structure extends under the first memory gate. A height of the inter-gate dielectric structure decreases along a direction extending from the first select gate to the first memory gate.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: May 23, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Ming Wu, Wei Cheng Wu, Shih-Chang Liu, Harry-Hak-Lay Chuang, Chia-Shiung Tsai
  • Publication number: 20230140961
    Abstract: Video processing methods include receiving input data of a current block in a current slice, determine determining whether one or more components of the current block satisfy one or more predefined criteria during partitioning, and applying a mode constraint to the current block only if the one or more components of the current block satisfy the one or more predefined criteria, wherein the mode constraint restricts all blocks within the current block to be processed by a same prediction mode when the current block is split into a plurality of blocks. The methods adaptively split the current block into one or more blocks, and pare one or more prediction mode syntax elements of a first block in the current block according to a constrained mode of the current block. The methods further encode the current block with the mode constraint.
    Type: Application
    Filed: January 5, 2023
    Publication date: May 11, 2023
    Inventors: Zhi-Yi LIN, Tzu-Der CHUANG, Ching-Yeh CHEN, Chia-Ming TSAI
  • Patent number: 11644296
    Abstract: A 3D measuring equipment and a 3D measuring method are provided. The 3D measuring equipment includes a base, a fixture, a measuring device, and a controller. The fixture is disposed on the base for an object to be measured to be disposed thereon. The fixture has a plurality of rods. The heights of the rods are adjustable. The measuring device is installed on the base and is movable relative to the fixture. The controller is connected to the measuring device and the fixture and configured to perform the following. The heights of the rods are adjusted according to 3D model data of the object to be measured to support the object to be measured. The measuring device is driven to move relative to the fixture to measure the object to be measured.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: May 9, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Chin-Chia Chang, Chia-Ching Lin, Yi-Tong Liu, Chia-Ming Tsai
  • Publication number: 20230119972
    Abstract: Video encoding methods and apparatuses for performing rate-distortion optimization by a hierarchical architecture include receiving input data associated with a current block in a current picture, determining a block partitioning structure to split the current block into coding blocks and determining a corresponding coding mode for each coding block by multiple Processing Element (PE) groups, and entropy encoding the coding blocks in the current block according to the coding modes determined by the PE groups. Each PE group has parallel PEs and is associated with a particular block size. The parallel PEs in each PE group test a number of coding modes on each partition or sub-partition of the current block to derive rate-distortion costs. The block partitioning structure and corresponding coding modes are then decided based on the rate-distortion costs derived by the PE groups.
    Type: Application
    Filed: January 18, 2022
    Publication date: April 20, 2023
    Inventors: Chia-Ming TSAI, Chun-Chia CHEN, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
  • Publication number: 20230122103
    Abstract: The present disclosure describes method to form a semiconductor device with a diffusion barrier layer. The method includes forming a gate dielectric layer on a fin structure, forming a work function stack on the gate dielectric layer, reducing a carbon concentration in the work function stack, forming a barrier layer on the work function stack, and forming a metal layer over the barrier layer. The barrier layer blocks a diffusion of impurities into the work function stack, the gate dielectric layer, and the fin structure.
    Type: Application
    Filed: November 7, 2022
    Publication date: April 20, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chandrashekhar Prakash SAVANT, Tien-Wei YU, Chia-Ming TSAI
  • Publication number: 20230087875
    Abstract: Image or video processing methods and apparatuses comprise receiving input data associated with a current picture or a current slice in the current picture, determining whether the current picture is a monochrome picture, conditionally signaling or parsing chroma deblocking parameters depending on whether the current picture is a monochrome picture, and encode or decode the current picture or current slice. The chroma deblocking parameters are used in a deblocking filter operation applied to chroma components of the current picture or current slice when the current picture is not a monochrome picture. A syntax element may be used to indicate derivation of chroma deblocking parameters, and based on a value of the syntax element, the chroma deblocking parameters are allowed to be explicitly signaled in or parsed from a syntax structure, or the chroma deblocking parameters are implicitly inferred.
    Type: Application
    Filed: February 25, 2021
    Publication date: March 23, 2023
    Inventors: Chia-Ming TSAI, Chih-Wei HSU, Shih-Ta HSIANG
  • Publication number: 20230065083
    Abstract: Low-latency video coding methods and apparatuses include receiving input data associated with a current Intra slice composed of Coding Tree Units (CTU), where each CTU includes luma and chroma Coding Tree Blocks (CTBs), partitioning each CTB into non-overlapping pipeline units, and encoding or decoding the CTUs in the current Intra slices by performing processing of chroma pipeline units after beginning processing of luma pipeline units in at least one pipeline stage. Each of the pipeline units is processed by one pipeline stage after another pipeline stage, and different pipeline stages process different pipeline units simultaneously. The pipeline stage in the low-latency video coding methods and apparatuses simultaneously processes one luma pipeline unit and at least one previous chroma pipeline unit within one pipeline unit time interval.
    Type: Application
    Filed: December 16, 2021
    Publication date: March 2, 2023
    Inventors: Chia-Ming TSAI, Chun-Chia CHEN, Chih-Wei HSU, Ching-Yeh CHEN, Tzu-Der CHUANG, Yu-Wen HUANG
  • Patent number: 11589050
    Abstract: Video processing methods comprise receiving input data of a current block, checking whether the current block is a root block by considering one or more predefined criteria, applying a mode constraint, a chroma split constraint, or both the mode and chroma split constraints to the current block if the current block is set to be a root block, and encoding or decoding the current block. The mode constraint restricts all blocks split from the current block to be processed by a same prediction mode and the chroma split constraints prohibits chroma components of the current block to be further partitioned while allowing a luma component of the current block to be partitioned into smaller blocks.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: February 21, 2023
    Assignee: HFI INNOVATION INC.
    Inventors: Zhi-Yi Lin, Tzu-Der Chuang, Ching-Yeh Chen, Chia-Ming Tsai
  • Patent number: 11552178
    Abstract: The present disclosure describes a method for the formation of gate stacks having two or more titanium-aluminum (TiAl) layers with different Al concentrations (e.g., different Al/Ti ratios). For example, a gate structure can include a first TiAl layer with a first Al/Ti ratio and a second TiAl layer with a second Al/Ti ratio greater than the first Al/Ti ratio of the first TiAl layer.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: January 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Wang, Chia-Ming Tsai, Ke-Chih Liu, Chandrashekhar Prakash Savant, Tien-Wei Yu
  • Publication number: 20230005796
    Abstract: The present disclosure describes a semiconductor device having metal boundary trench isolation with electrically conductive intermediate structures acting as a metal diffusion barrier. The semiconductor structure includes a first fin structure and a second fin structure on a substrate, an insulating layer between the first and second fin structures, a gate dielectric layer on the insulating layer and the first and second fin structures, and a first work function stack and a second work function stack on the gate dielectric layer. The first work function stack is over the first fin structure and a first portion of the insulating layer, and the second work function stack is over the second fin structure and a second portion of the insulating layer adjacent to the first portion. The semiconductor structure further includes a conductive intermediate structure on the gate dielectric layer and between the first and second work function stacks.
    Type: Application
    Filed: July 26, 2022
    Publication date: January 5, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chandrashekhar Prakash SAVANT, Chia-Ming TSAI, Yuh-Ta FAN, Tien-Wei YU
  • Publication number: 20230007281
    Abstract: Video processing methods and apparatuses for processing a current block in a current picture by reference picture resampling include receiving input data of the current block, determining a scaling window of the current picture and a scaling window of a reference picture. The current picture and reference picture may have different scaling window sizes. A ratio between a scaling window width, height, or size of the current picture and a scaling window width, height, or size of the reference picture is constrained to be within a ratio constraint. A reference block is generated from the reference picture according to the ratio, and used to encode or decode the current block.
    Type: Application
    Filed: December 10, 2020
    Publication date: January 5, 2023
    Inventors: Tzu-Der CHUANG, Chih-Wei HSU, Ching-Yeh CHEN, Chia-Ming TSAI, Chun-Chia CHEN, Olena CHUBACH, Lulin CHEN, Yu-Wen HUANG
  • Patent number: 11536811
    Abstract: A distance measuring device includes a pulsed laser source, a light receiving unit and a computing module. The pulsed laser source emits a laser pulse to a target in accordance with a predetermined period. The light receiving unit has a photon receiving type of light receiving element that receives incident light and outputs a binary pulse, and the binary pulse is used to indicate whether a photon receiving event occurs. The computing module is configured to receive the binary pulse and determine whether an inter-period coincidence event occurs, and the inter-period coincidence event is defined by detecting a plurality of photon receiving events exceeding a predetermined count, on relative positions in a predetermined period number of the predetermined periods. If the calculation module determines that the inter-period coincidence event occurs, a distance of the target is calculated according to time information related to the inter-period coincidence event.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: December 27, 2022
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Chia-Ming Tsai, Yu-Wei Chen, Yung-Chien Liu
  • Publication number: 20220385889
    Abstract: A method and apparatus for video coding using Intra prediction are disclosed. In one method, a first prediction sample in an immediately right column of the current block and a second prediction sample in an immediately below row of the current block are derived using angular prediction. The first prediction sample and a left column reference sample in the same row as the first prediction sample are interpolated to generate a horizontal predictor. The second prediction sample and an above-row reference sample in the same column as the second prediction sample are interpolated to generate a vertical predictor. The vertical predictor and the horizontal predictor are linearly combined to generate an angular-planar prediction sample. In another method, a first predictor is generated using angular prediction and a second predictor is generated using planar prediction. The first predictor and the second predictor are linearly combined to generate a fused Intra predictor.
    Type: Application
    Filed: August 4, 2022
    Publication date: December 1, 2022
    Inventors: Chia-Ming TSAI, Han HUANG, Chih-Wei HSU, Yu-Wen HUANG
  • Patent number: 11516513
    Abstract: In one method, the current block is partitioned into multiple final sub-blocks using one or more stages of sub-tree partition comprising ternary tree partition and at least one other-type partition, where ternary partition tree is excluded from the sub-tree partition if a current sub-tree depth associated with a current sub-block is greater than a first threshold and the first threshold is an integer greater than or equal to 1. In another method, if a test condition is satisfied, the current block is encoded or decoded using a current Inter mode selected from a modified group of Inter tools, where the modified group of Inter tools is derived from an initial group of Inter tools by removing one or more first Inter tools from the initial group of Inter tools, replacing one or more second Inter tools with one or more complexity-reduced Inter tools, or both.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: November 29, 2022
    Assignee: MEDIATEK INC.
    Inventors: Chun-Chia Chen, Chia-Ming Tsai, Yu-Chi Su, Chen-Yen Lai, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang, Han Huang
  • Patent number: 11495463
    Abstract: The present disclosure describes method to form a semiconductor device with a diffusion barrier layer. The method includes forming a gate dielectric layer on a fin structure, forming a work function stack on the gate dielectric layer, reducing a carbon concentration in the work function stack, forming a barrier layer on the work function stack, and forming a metal layer over the barrier layer. The barrier layer blocks a diffusion of impurities into the work function stack, the gate dielectric layer, and the fin structure.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: November 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chandrashekhar Prakash Savant, Tien-Wei Yu, Chia-Ming Tsai
  • Publication number: 20220352160
    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first work function adjustment material layer is formed over the gate dielectric layer, an adhesion enhancement layer is formed on the first work function adjustment material layer, a mask layer including an antireflective organic material layer is formed on the adhesion enhancement layer, and the adhesion enhancement layer and the first work function adjustment material layer are patterned by using the mask layer as an etching mask. The adhesion enhancement layer has a higher adhesion strength to the antireflective organic material layer than the first work function adjustment material layer.
    Type: Application
    Filed: July 14, 2022
    Publication date: November 3, 2022
    Inventors: Shahaji B. MORE, Chandrashekhar Prakash SAVANT, Tien-Wei YU, Chia-Ming TSAI
  • Publication number: 20220336289
    Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes a fin structure disposed on a substrate, and first and second gate structures on the fin structure. The first and second gate structures includes first and second interfacial oxide layers, respectively, first and second high-K gate dielectric layers disposed on the first and second TO layers, respectively, and first and second dopant control layers disposed on the first and second HK gate dielectric layers, respectively. The second dopant control layer has a silicon-to-metal atomic concentration ratio greater than an Si-to-metal atomic concentration ratio of the first dopant control layer. The semiconductor further includes first and second work function metal layers disposed on the first and second dopant control layers, respectively, and first and second gate metal fill layers disposed on the first and second work function metal layers, respectively.
    Type: Application
    Filed: July 6, 2022
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chandrashekhar Prakash Savant, Chia-Ming Tsai, Tien-Wei Yu
  • Patent number: 11477444
    Abstract: A video processing method for a video encoder or decoder comprises receiving input data of a current chroma block in a current picture coded in a 4:2:2 color format, determining a luma mode of a luma block corresponding to the current chroma block, mapping the luma mode to a mapped intra mode of the current chroma block, selectively replacing the mapped intra mode by wide angle intra prediction mapping based on a width to height ratio of the current chroma block, deriving an intra predictor according to the mapped intra mode after wide angle intra prediction mapping, and encoding or decoding the current chroma block according to the intra predictor. The mapped intra mode is mode 57 when the luma mode is mode 61 and the mapped intra mode is mode 55 when the luma mode is mode 57.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: October 18, 2022
    Assignee: HFI INNOVATION INC.
    Inventors: Man-Shu Chiang, Chia-Ming Tsai, Chih-Wei Hsu
  • Publication number: 20220320320
    Abstract: A semiconductor device includes a substrate, a semiconductor fin, a gate structure, and source/drain structures. The semiconductor fin extends upwardly from the substrate. The gate structure is across the semiconductor fin and includes a high-k dielectric layer over the semiconductor fin, a fluorine-containing work function layer over the high-k dielectric layer and comprising fluorine, a tungsten-containing layer over the fluorine-containing work function layer, and a metal gate electrode over the tungsten-containing layer. The source/drain structures are on the semiconductor fin and at opposite sides of the gate structure.
    Type: Application
    Filed: June 17, 2022
    Publication date: October 6, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chandrashekhar P. SAVANT, Tien-Wei YU, Ke-Chih LIU, Chia-Ming TSAI