Patents by Inventor Chia-Ming Tsai

Chia-Ming Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12016041
    Abstract: A method performed by a User Equipment (UE) includes receiving, through Radio Resource Control (RRC) signaling from a Base Station (BS), an indication indicating a dormancy cell group having at least a first serving cell and a second serving cell, receiving, through Physical Layer (PHY) signaling from the BS, a signal associated with a specific Downlink Control Information (DCI) format indicating a dormant behavior applicable to all serving cells in the dormancy cell group, wherein the signal indicates the dormant behavior via a single bit, applying the dormant behavior to the first serving cell and the second serving cell when the signal indicates that the dormant behavior is to be activated, and not applying the dormant behavior to the first serving cell and the second serving cell when the signal indicates that the dormant behavior is to be deactivated.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: June 18, 2024
    Assignee: FG Innovation Company Limited
    Inventors: Hsin-Hsi Tsai, Chia-Hung Wei, Chie-Ming Chou
  • Publication number: 20240194663
    Abstract: A semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer.
    Type: Application
    Filed: February 21, 2024
    Publication date: June 13, 2024
    Inventors: I-SHENG CHEN, YI-JING LI, CHIA-MING HSU, WAN-LIN TSAI, CLEMENT HSINGJEN WANN
  • Patent number: 12004187
    Abstract: A method performed by a UE for repetition transmissions is provided. The method includes receiving DCI scheduling an uplink transmission; identifying a DCI format of the DCI; selecting, from a plurality of sets of preconfigured values, a set of preconfigured values that is mapped to the DCI format; and determining a number of times the uplink transmission is required to be repeated from the selected set of preconfigured values. A UE applying the same method is also provided.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: June 4, 2024
    Assignee: FG Innovation Company Limited
    Inventors: Chia-Hung Wei, Heng-Li Chin, Hsin-Hsi Tsai, Chie-Ming Chou
  • Publication number: 20240179311
    Abstract: A method and apparatus for block partition are disclosed. If a cross-colour component prediction mode is allowed, the luma block and the chroma block are partitioned into one or more luma leaf blocks and chroma leaf blocks. If a cross-colour component prediction mode is allowed, whether to enable an LM (Linear Model) mode for a target chroma leaf block is determined based on a first split type applied to an ancestor chroma node of the target chroma leaf block and a second split type applied to a corresponding ancestor luma node. According to another method, after the luma block and the chroma block are partitioned using different partition tress, determine whether one or more exception conditions to allow an LM for a target chroma leaf block are satisfied when the chroma partition tree uses a different split type, a different partition direction, or both from the luma partition tree.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Inventors: Chia-Ming TSAI, Tzu-Der CHUANG, Chih-Wei HSU, Ching-Yeh CHEN, Zhi-Yi LIN
  • Patent number: 11997597
    Abstract: A method for a user equipment (UE) monitoring a physical downlink control channel (PDCCH) for power saving signaling is disclosed. The method comprises receiving a discontinuous reception (DRX) configuration from a base station (BS) to configure the UE to monitor a scheduling signal on the PDCCH within a DRX active time, and receiving a configuration from the BS to configure the UE to monitor the power saving signaling on the PDCCH and instructing the UE to wake up for monitoring the scheduling signal in the DRX active time, wherein the configuration includes a time in milliseconds prior to a start of a DRX on-duration time, and instructs the UE to start monitoring the PDCCH for the power saving signaling.
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: May 28, 2024
    Assignee: Hannibal IP LLC
    Inventors: Yu-Hsin Cheng, Hsin-Hsi Tsai, Chia-Hao Yu, Chie-Ming Chou
  • Publication number: 20240172122
    Abstract: A method for a UE to monitor a PDCCH comprises receiving a first configuration from a base station to configure the UE with a first search space of the PDCCH, where the first search space is used for monitoring a scheduling signal used for indicating scheduling information, receiving a second configuration from the base station to configure the UE with a second search space of the PDCCH, wherein the second search space is used for monitoring a power saving signal used for indicating wake-up information associated with a DRX functionality, monitoring the first search space in response to the UE being in a DRX active time of the DRX functionality, wherein the DRX active time is a time during which the UE monitors the PDCCH, and not monitoring the second search space in response to the UE being in the DRX active time of the DRX functionality.
    Type: Application
    Filed: November 16, 2023
    Publication date: May 23, 2024
    Inventors: Hsin-Hsi Tsai, Chia-Hung Wei, Chie-Ming Chou
  • Publication number: 20240170326
    Abstract: A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An etch stop layer is formed on the sacrificial substrate. A portion of the etch stop layer is oxidized to form an oxide layer between the sacrificial substrate and the remaining etch stop layer. A capping layer is formed on the remaining etch stop layer. A device layer is formed on the capping layer. A first etching process is performed to remove the sacrificial substrate. A second etching process is performed to remove the oxide layer. A third etching process is performed to remove the remaining etch stop layer. A power rail is formed on the capping layer opposite to the device layer.
    Type: Application
    Filed: January 25, 2024
    Publication date: May 23, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Chen, Kuei-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai
  • Patent number: 11985314
    Abstract: Video processing methods and apparatuses in a video encoding or decoding system for processing out-of-bounds nodes in a current picture. An out-of-bounds node is a coding tree node with a block region across a current picture boundary. The video processing method or apparatus determines an inferred splitting type, applies the inferred splitting type to split the out-of-bounds node into child blocks, adaptively splits each child block into one or multiple leaf blocks, and encodes or decodes the leaf blocks in the out-of-bounds node inside the current picture. The inferred splitting type for partitioning out-of-bounds nodes in an inter slice, picture, or tile is the same as the inferred splitting type for partitioning out-of-bounds nodes in an intra slice, picture, or tile.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: May 14, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang, Shih-Ta Hsiang
  • Publication number: 20240152671
    Abstract: A violation checking method includes generating a violation log report for a design, classifying violation logs in the violation log report into high-risk logs and low-risk logs by a machine learning model, reviewing the high-risk logs, and modifying the design if at least one bug is identified in the high-risk logs.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 9, 2024
    Applicant: MEDIATEK INC.
    Inventors: Chi-Ming Lee, Chung-An Wang, Cheok Yan Goh, Chia-Cheng Tsai, Chien-Hsin Yeh, Chia-Shun Yeh, Chin-Tang Lai
  • Patent number: 11978675
    Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chandrashekhar Prakash Savant, Chia-Ming Tsai, Ming-Te Chen, Tien-Wei Yu
  • Publication number: 20240143887
    Abstract: A method includes: receiving a design layout comprising a feature extending in a peripheral region and a central region of the design layout; determining compensation values associated with a pellicle assembly and the peripheral region according to an exposure distribution in an exposure field of a workpiece; and adjusting the design layout according to the compensation values. The modifying of the shape of the feature according to the compensation values includes: partitioning the peripheral region into compensation zones; and adjusting line widths in the compensation zones of the feature according to the compensation values associated with the respective compensation zones.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 2, 2024
    Inventors: CHI-TA LU, CHIA-HUI LIAO, YIHUNG LIN, CHI-MING TSAI
  • Publication number: 20240145570
    Abstract: A semiconductor device includes a gate structure disposed over a channel region and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, one or more work function adjustment material layers over the gate dielectric layer, and a metal gate electrode layer over the one or more work function adjustment material layers. The one or more work function adjustment layers includes an aluminum containing layer, and a diffusion barrier layer is disposed at at least one of a bottom portion and a top portion of the aluminum containing layer. The diffusion barrier layer is one or more of a Ti-rich layer, a Ti-doped layer, a Ta-rich layer, a Ta-doped layer and a Si-doped layer.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. MORE, Chandrashekhar Prakash SAVANT, Tien-Wei YU, Chia-Ming TSAI
  • Publication number: 20240129167
    Abstract: A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.
    Type: Application
    Filed: September 18, 2023
    Publication date: April 18, 2024
    Applicant: MEDIATEK INC.
    Inventors: Chung-Hsien Tsai, Che-Yu Chiang, Yu-Ting Liu, Tsung-Lin Lee, Chia-Sheng Peng, Ting-Ming Yang
  • Patent number: 11955374
    Abstract: A method of forming a semiconductor-on-insulator (SOI) substrate includes: forming a first dielectric layer on a first substrate; forming a buffer layer on a second substrate; forming a semiconductor cap on the buffer layer over the second substrate; forming a cleavage plane in the buffer layer; forming a second dielectric layer on the semiconductor cap after forming the cleavage plane; bonding the second dielectric layer on the second substrate to the first dielectric layer on the first substrate; performing a splitting process along the cleavage plane in the buffer layer; removing a first split buffer layer from the semiconductor cap; and removing a second split buffer layer from the second substrate.
    Type: Grant
    Filed: August 29, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Chen, Eugene I-Chun Chen, Chia-Shiung Tsai
  • Publication number: 20240113254
    Abstract: A semiconductor light emitting device includes a multi-quantum-well structure, a first capping layer, a second capping layer, and an electron barrier layer stacked in order. The multi-quantum-well structure includes a plurality of alternately-stacked potential barrier layers and potential well layers. The first capping layer is a semiconductor layer, and the second capping layer is a p-doped semiconductor layer. Each of the first and second capping layers has an aluminum mole fraction larger than that of each of the potential barrier layers, and the aluminum mole fraction of the first capping layer is larger than that of at least a portion of the electron barrier layer. A method for preparing the semiconductor light emitting device is also provided.
    Type: Application
    Filed: December 15, 2023
    Publication date: April 4, 2024
    Inventors: Yung-Ling LAN, Chan-Chan LING, Chi-Ming TSAI, Chia-Hung CHANG
  • Patent number: 11942467
    Abstract: A semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: I-Sheng Chen, Yi-Jing Li, Chia-Ming Hsu, Wan-Lin Tsai, Clement Hsingjen Wann
  • Patent number: 11943030
    Abstract: A method for wireless communication performed by a user equipment (UE) is provided. The UE includes a plurality of antenna panels. The method includes transmitting, to a Base Station (BS), a UE capability message that includes a number of the plurality of antenna panels; and transmitting, to the BS, a panel report that includes information of the plurality of antenna panels, the information associated with at least one of a Synchronization Signal Block (SSB) and a Channel State Information Reference Signal (CSI-RS).
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: March 26, 2024
    Assignee: FG Innovation Company Limited
    Inventors: Chia-Hao Yu, Hsin-Hsi Tsai, Chie-Ming Chou
  • Publication number: 20240094783
    Abstract: An example computing device includes a first housing portion, a second housing portion moveably connected to the first housing portion, a link to selectively secure the second housing portion to the first housing portion to inhibit movement of the second housing portion relative to the first housing portion, and a shape-memory alloy element to release the link to allow the second housing portion to move relative to the first housing portion.
    Type: Application
    Filed: September 15, 2022
    Publication date: March 21, 2024
    Inventors: Yu-Wen LIN, Chia-Ming TSAI, Shih-Jen CHOU, John Joseph GRODEN
  • Publication number: 20240097009
    Abstract: A semiconductor structure includes a substrate, a channel region, a gate structure, and source/drain regions. The channel region is over the substrate. The gate structure is over the channel region, and includes a high-k dielectric layer, a tungsten layer over the high-k dielectric layer, and a fluorine-containing work function layer over the tungsten layer. The source/drain regions are at opposite sides of the channel region.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chandrashekhar P. SAVANT, Tien-Wei YU, Ke-Chih LIU, Chia-Ming TSAI
  • Patent number: 11931187
    Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: March 19, 2024
    Assignees: Chang Gung Medical Foundation Chang Gung Memorial Hospital at Keelung, Chang Gung Memorial Hospital, Linkou, Chang Gung University
    Inventors: Jiun-Jie Wang, Yi-Hsin Weng, Shu-Hang Ng, Jur-Shan Cheng, Yi-Ming Wu, Yao-Liang Chen, Wey-Yil Lin, Chin-Song Lu, Wen-Chuin Hsu, Chia-Ling Chen, Yi-Chun Chen, Sung-Han Lin, Chih-Chien Tsai