Patents by Inventor Chia-Ming Tsai

Chia-Ming Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230377994
    Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.
    Type: Application
    Filed: August 3, 2023
    Publication date: November 23, 2023
    Inventors: Chandrashekhar Prakash SAVANT, Chia-Ming Tsai, Ming-Te Chen, Tien-Wei Yu
  • Patent number: 11800102
    Abstract: Low-latency video coding methods and apparatuses include receiving input data associated with a current Intra slice composed of Coding Tree Units (CTU), where each CTU includes luma and chroma Coding Tree Blocks (CTBs), partitioning each CTB into non-overlapping pipeline units, and encoding or decoding the CTUs in the current Intra slices by performing processing of chroma pipeline units after beginning processing of luma pipeline units in at least one pipeline stage. Each of the pipeline units is processed by one pipeline stage after another pipeline stage, and different pipeline stages process different pipeline units simultaneously. The pipeline stage in the low-latency video coding methods and apparatuses simultaneously processes one luma pipeline unit and at least one previous chroma pipeline unit within one pipeline unit time interval.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: October 24, 2023
    Assignee: MEDIATEK INC.
    Inventors: Chia-Ming Tsai, Chun-Chia Chen, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Patent number: 11784187
    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first work function adjustment material layer is formed over the gate dielectric layer, an adhesion enhancement layer is formed on the first work function adjustment material layer, a mask layer including an antireflective organic material layer is formed on the adhesion enhancement layer, and the adhesion enhancement layer and the first work function adjustment material layer are patterned by using the mask layer as an etching mask. The adhesion enhancement layer has a higher adhesion strength to the antireflective organic material layer than the first work function adjustment material layer.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: October 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Chandrashekhar Prakash Savant, Tien-Wei Yu, Chia-Ming Tsai
  • Patent number: 11765365
    Abstract: Method and apparatus for constrained de-blocking filter are disclosed. One method receives input data related to a current block in a current picture at a video encoder side or a video bitstream determines a block boundary of the current block and sub-block boundaries inside the current block, wherein the current block is partitioned into a plurality of sub-blocks using sub-block mode prediction. The method then applies de-blocking process to a reconstructed current block corresponding to the current block to result in a current filtered-reconstructed block, wherein said applying the de-blocking process to the current block comprises applying the de-blocking process to the sub-block boundaries inside the current filtered-reconstructed block, and generates a filtered decoded picture including the current filtered-reconstructed block.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: September 19, 2023
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Publication number: 20230268231
    Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 24, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chandrashekhar Prakash SAVANT, Chia-Ming TSAI, Ming-Te Chen, Shih-Chi Lin, Zack Chong, Tien-Wei Yu
  • Patent number: 11670553
    Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: June 6, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chandrashekhar Prakash Savant, Chia-Ming Tsai, Ming-Te Chen, Shih-Chi Lin, Zack Chong, Tien-Wei Yu
  • Publication number: 20230140961
    Abstract: Video processing methods include receiving input data of a current block in a current slice, determine determining whether one or more components of the current block satisfy one or more predefined criteria during partitioning, and applying a mode constraint to the current block only if the one or more components of the current block satisfy the one or more predefined criteria, wherein the mode constraint restricts all blocks within the current block to be processed by a same prediction mode when the current block is split into a plurality of blocks. The methods adaptively split the current block into one or more blocks, and pare one or more prediction mode syntax elements of a first block in the current block according to a constrained mode of the current block. The methods further encode the current block with the mode constraint.
    Type: Application
    Filed: January 5, 2023
    Publication date: May 11, 2023
    Inventors: Zhi-Yi LIN, Tzu-Der CHUANG, Ching-Yeh CHEN, Chia-Ming TSAI
  • Patent number: 11644296
    Abstract: A 3D measuring equipment and a 3D measuring method are provided. The 3D measuring equipment includes a base, a fixture, a measuring device, and a controller. The fixture is disposed on the base for an object to be measured to be disposed thereon. The fixture has a plurality of rods. The heights of the rods are adjustable. The measuring device is installed on the base and is movable relative to the fixture. The controller is connected to the measuring device and the fixture and configured to perform the following. The heights of the rods are adjusted according to 3D model data of the object to be measured to support the object to be measured. The measuring device is driven to move relative to the fixture to measure the object to be measured.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: May 9, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Chin-Chia Chang, Chia-Ching Lin, Yi-Tong Liu, Chia-Ming Tsai
  • Publication number: 20230122103
    Abstract: The present disclosure describes method to form a semiconductor device with a diffusion barrier layer. The method includes forming a gate dielectric layer on a fin structure, forming a work function stack on the gate dielectric layer, reducing a carbon concentration in the work function stack, forming a barrier layer on the work function stack, and forming a metal layer over the barrier layer. The barrier layer blocks a diffusion of impurities into the work function stack, the gate dielectric layer, and the fin structure.
    Type: Application
    Filed: November 7, 2022
    Publication date: April 20, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chandrashekhar Prakash SAVANT, Tien-Wei YU, Chia-Ming TSAI
  • Publication number: 20230119972
    Abstract: Video encoding methods and apparatuses for performing rate-distortion optimization by a hierarchical architecture include receiving input data associated with a current block in a current picture, determining a block partitioning structure to split the current block into coding blocks and determining a corresponding coding mode for each coding block by multiple Processing Element (PE) groups, and entropy encoding the coding blocks in the current block according to the coding modes determined by the PE groups. Each PE group has parallel PEs and is associated with a particular block size. The parallel PEs in each PE group test a number of coding modes on each partition or sub-partition of the current block to derive rate-distortion costs. The block partitioning structure and corresponding coding modes are then decided based on the rate-distortion costs derived by the PE groups.
    Type: Application
    Filed: January 18, 2022
    Publication date: April 20, 2023
    Inventors: Chia-Ming TSAI, Chun-Chia CHEN, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
  • Publication number: 20230087875
    Abstract: Image or video processing methods and apparatuses comprise receiving input data associated with a current picture or a current slice in the current picture, determining whether the current picture is a monochrome picture, conditionally signaling or parsing chroma deblocking parameters depending on whether the current picture is a monochrome picture, and encode or decode the current picture or current slice. The chroma deblocking parameters are used in a deblocking filter operation applied to chroma components of the current picture or current slice when the current picture is not a monochrome picture. A syntax element may be used to indicate derivation of chroma deblocking parameters, and based on a value of the syntax element, the chroma deblocking parameters are allowed to be explicitly signaled in or parsed from a syntax structure, or the chroma deblocking parameters are implicitly inferred.
    Type: Application
    Filed: February 25, 2021
    Publication date: March 23, 2023
    Inventors: Chia-Ming TSAI, Chih-Wei HSU, Shih-Ta HSIANG
  • Publication number: 20230065083
    Abstract: Low-latency video coding methods and apparatuses include receiving input data associated with a current Intra slice composed of Coding Tree Units (CTU), where each CTU includes luma and chroma Coding Tree Blocks (CTBs), partitioning each CTB into non-overlapping pipeline units, and encoding or decoding the CTUs in the current Intra slices by performing processing of chroma pipeline units after beginning processing of luma pipeline units in at least one pipeline stage. Each of the pipeline units is processed by one pipeline stage after another pipeline stage, and different pipeline stages process different pipeline units simultaneously. The pipeline stage in the low-latency video coding methods and apparatuses simultaneously processes one luma pipeline unit and at least one previous chroma pipeline unit within one pipeline unit time interval.
    Type: Application
    Filed: December 16, 2021
    Publication date: March 2, 2023
    Inventors: Chia-Ming TSAI, Chun-Chia CHEN, Chih-Wei HSU, Ching-Yeh CHEN, Tzu-Der CHUANG, Yu-Wen HUANG
  • Patent number: 11589050
    Abstract: Video processing methods comprise receiving input data of a current block, checking whether the current block is a root block by considering one or more predefined criteria, applying a mode constraint, a chroma split constraint, or both the mode and chroma split constraints to the current block if the current block is set to be a root block, and encoding or decoding the current block. The mode constraint restricts all blocks split from the current block to be processed by a same prediction mode and the chroma split constraints prohibits chroma components of the current block to be further partitioned while allowing a luma component of the current block to be partitioned into smaller blocks.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: February 21, 2023
    Assignee: HFI INNOVATION INC.
    Inventors: Zhi-Yi Lin, Tzu-Der Chuang, Ching-Yeh Chen, Chia-Ming Tsai
  • Patent number: 11552178
    Abstract: The present disclosure describes a method for the formation of gate stacks having two or more titanium-aluminum (TiAl) layers with different Al concentrations (e.g., different Al/Ti ratios). For example, a gate structure can include a first TiAl layer with a first Al/Ti ratio and a second TiAl layer with a second Al/Ti ratio greater than the first Al/Ti ratio of the first TiAl layer.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: January 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Wang, Chia-Ming Tsai, Ke-Chih Liu, Chandrashekhar Prakash Savant, Tien-Wei Yu
  • Publication number: 20230007281
    Abstract: Video processing methods and apparatuses for processing a current block in a current picture by reference picture resampling include receiving input data of the current block, determining a scaling window of the current picture and a scaling window of a reference picture. The current picture and reference picture may have different scaling window sizes. A ratio between a scaling window width, height, or size of the current picture and a scaling window width, height, or size of the reference picture is constrained to be within a ratio constraint. A reference block is generated from the reference picture according to the ratio, and used to encode or decode the current block.
    Type: Application
    Filed: December 10, 2020
    Publication date: January 5, 2023
    Inventors: Tzu-Der CHUANG, Chih-Wei HSU, Ching-Yeh CHEN, Chia-Ming TSAI, Chun-Chia CHEN, Olena CHUBACH, Lulin CHEN, Yu-Wen HUANG
  • Publication number: 20230005796
    Abstract: The present disclosure describes a semiconductor device having metal boundary trench isolation with electrically conductive intermediate structures acting as a metal diffusion barrier. The semiconductor structure includes a first fin structure and a second fin structure on a substrate, an insulating layer between the first and second fin structures, a gate dielectric layer on the insulating layer and the first and second fin structures, and a first work function stack and a second work function stack on the gate dielectric layer. The first work function stack is over the first fin structure and a first portion of the insulating layer, and the second work function stack is over the second fin structure and a second portion of the insulating layer adjacent to the first portion. The semiconductor structure further includes a conductive intermediate structure on the gate dielectric layer and between the first and second work function stacks.
    Type: Application
    Filed: July 26, 2022
    Publication date: January 5, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chandrashekhar Prakash SAVANT, Chia-Ming TSAI, Yuh-Ta FAN, Tien-Wei YU
  • Patent number: 11536811
    Abstract: A distance measuring device includes a pulsed laser source, a light receiving unit and a computing module. The pulsed laser source emits a laser pulse to a target in accordance with a predetermined period. The light receiving unit has a photon receiving type of light receiving element that receives incident light and outputs a binary pulse, and the binary pulse is used to indicate whether a photon receiving event occurs. The computing module is configured to receive the binary pulse and determine whether an inter-period coincidence event occurs, and the inter-period coincidence event is defined by detecting a plurality of photon receiving events exceeding a predetermined count, on relative positions in a predetermined period number of the predetermined periods. If the calculation module determines that the inter-period coincidence event occurs, a distance of the target is calculated according to time information related to the inter-period coincidence event.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: December 27, 2022
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Chia-Ming Tsai, Yu-Wei Chen, Yung-Chien Liu
  • Publication number: 20220385889
    Abstract: A method and apparatus for video coding using Intra prediction are disclosed. In one method, a first prediction sample in an immediately right column of the current block and a second prediction sample in an immediately below row of the current block are derived using angular prediction. The first prediction sample and a left column reference sample in the same row as the first prediction sample are interpolated to generate a horizontal predictor. The second prediction sample and an above-row reference sample in the same column as the second prediction sample are interpolated to generate a vertical predictor. The vertical predictor and the horizontal predictor are linearly combined to generate an angular-planar prediction sample. In another method, a first predictor is generated using angular prediction and a second predictor is generated using planar prediction. The first predictor and the second predictor are linearly combined to generate a fused Intra predictor.
    Type: Application
    Filed: August 4, 2022
    Publication date: December 1, 2022
    Inventors: Chia-Ming TSAI, Han HUANG, Chih-Wei HSU, Yu-Wen HUANG
  • Patent number: 11516513
    Abstract: In one method, the current block is partitioned into multiple final sub-blocks using one or more stages of sub-tree partition comprising ternary tree partition and at least one other-type partition, where ternary partition tree is excluded from the sub-tree partition if a current sub-tree depth associated with a current sub-block is greater than a first threshold and the first threshold is an integer greater than or equal to 1. In another method, if a test condition is satisfied, the current block is encoded or decoded using a current Inter mode selected from a modified group of Inter tools, where the modified group of Inter tools is derived from an initial group of Inter tools by removing one or more first Inter tools from the initial group of Inter tools, replacing one or more second Inter tools with one or more complexity-reduced Inter tools, or both.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: November 29, 2022
    Assignee: MEDIATEK INC.
    Inventors: Chun-Chia Chen, Chia-Ming Tsai, Yu-Chi Su, Chen-Yen Lai, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang, Han Huang
  • Patent number: 11495463
    Abstract: The present disclosure describes method to form a semiconductor device with a diffusion barrier layer. The method includes forming a gate dielectric layer on a fin structure, forming a work function stack on the gate dielectric layer, reducing a carbon concentration in the work function stack, forming a barrier layer on the work function stack, and forming a metal layer over the barrier layer. The barrier layer blocks a diffusion of impurities into the work function stack, the gate dielectric layer, and the fin structure.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: November 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chandrashekhar Prakash Savant, Tien-Wei Yu, Chia-Ming Tsai