Abstract: A printer circuit board (PCB) includes a voltage regulator module (VRM) and a body. The VRM supplies power to a first load and a second load. A decoupling circuit is set on one side of the first load, and the decoupling circuit is electronically connected to the first load. The body includes a multi-layer circuit board. The VRM, the first load, and the second load are positioned on one layer of the circuit board, where the VRM is electronically connected to the first load, but the VRM and the first load are electronically disconnected with the second load. The VRM, the first load, and the second load two are positioned on two other layers of the circuit board, where the first load is electronically connected to the second load, but the first load and the second load are electronically disconnected to the VRM.

Abstract: A device and a method reads a circuit printed circuit (PCB) layout file, extracts arrangement information of all the interference source components and signal transmission lines of the PCB layout file, and selects a interference source component from the PCB layout file, then determines if there is any signal transmission line is laid under the selected interference source component.

Abstract: A computer-based method and a computing device for checking stub lengths of via stubs of a printed circuit board (PCB) layout are provided. The computing device displays a check interface, selects signal transmission line from a currently run PCB layout through the check interface, receives a reference stub length input through the check interface, and determines the actual stub length of each via stub of each via each selected signal transmission line connected to. The computing device further determines that a design of one via stub satisfies the design standards, if the actual stub length of the one stub via is less than or equal to the reference length, and determines that a design of one via stub does not satisfy the design standards if the actual stub length of the one via stub is greater than the reference stub length.

Abstract: A computer-based method and a computing device for checking differential pairs of a printed circuit board layout are provided. The computing device determines the via pitch between switching vias of a differential pair according to the coordinates of the centers of the switching vias, determines the via gap between the switching vias of adjacent two differential pairs according to the radius and the coordinates of the centers of the switching vias, and determines that the switching vias does not satisfy design standards if the via pitch does not fall in an input via pitch range, or the via gap does not fall in an input via gap range.

Abstract: In a computing device, computerized method, and a non-transitory storage medium, plug-in capacitors are selected from capacitors in a wiring diagram according pin information of the capacitors. A straight line is constructed for each of the plug-in capacitors according to size of holes where pins of the plug-in capacitor are to be inserted into. Paths of all transmission lines in the wiring diagram are obtained, and a determination of, whether any of the paths has at least one intersection point with at least one constructed straight line, is made. One or more paths, which have at least one intersection point with at least one constructed straight line, are recorded into a path list. The path list is then outputted using the computing device.

Abstract: In a method for checking layout of a printed circuit board (PCB) using an electronic device, a signal line is selected from a layout diagram of the PCB. The method searches for signal lines which have an acute angle when deviating from a straight line in the layout diagram of the PCB. The method further locates attribute data of the searched signal lines in the layout diagram of the PCB, and displays the attribute data of the searched signal lines on a display device of the electronic device.

Abstract: A printed circuit board includes an insulation layer and a signal layer attached to the insulation layer. The signal layer includes a pair of differential transmission lines. Width W of each of the differential transmission lines is changed according to change of space S between the differential transmission lines, based on the following formula: W = C ? ? 1 × H × ( C ? ? 2 × H 0.8 ? W 0 + T ) C ? ? 3 × ? C ? ? 4 × S 0 H - 1 1 - C ? ? 3 × ? C ? ? 4 × S H - 1.25 ? T In above formula, C1=7.475, C2=5.98, C3=0.48, C4=?0.96, H is a thickness of the insulation layer, W0 is an original width of each of the differential transmission lines, and S0 is an original space between the differential transmission lines, and T is a thickness of each of the differential transmission lines.

Abstract: A computer-based method and a computing device for checking signal transmission lines of a printed circuit board (PCB) layout are provided. The computing device identifies differential pairs in a currently run PCB layout according to an information file for the currently run PCB layout, checks whether any signal transmission line is routed between switching vias of each differential pair according to the information file for the currently run PCB layout, and displays a routing error window to display information of each misrouted signal transmission line.

Abstract: A computer-based method and a computing device for checking stub lengths of via stubs of a printed circuit board (PCB) layout are provided. The computing device displays a check interface, selects signal transmission line from a currently run PCB layout through the check interface, receives a reference stub length input through the check interface, and determines the actual stub length of each via stub of each via each selected signal transmission line connected to. The computing device further determines that a design of one via stub satisfies the design standards, if the actual stub length of the one stub via is less than or equal to the reference length, and determines that a design of one via stub does not satisfy the design standards if the actual stub length of the one via stub is greater than the reference stub length.

Abstract: In a method for verifying a printed circuit board (PCB) layout using a computing device, a PCB simulation file is obtained from a storage device of the computing device, and a PCB image is displayed on a display device according to the PCB simulation file. The PCB image includes multiple signal lines and switching voltage regulator nodes (SVRN). A SVRN to be checked is selected from the PCB image, and all signal lines around the SVRN are searched. The method calculates a layout distance between the selected SVRN and each of the searched signal lines, and generates a graphical window interface to position a signal line whose layout distance is equal to or less than the minimum distance. The method further modifies the layout of the positioned signal line to satisfy a layout design specification by increasing the layout distance to the minimum distance.

Abstract: A circuit topology for multiple loads includes a driving terminal, first and second signal receiving terminals, and a capacitor. The driving terminal is connected to a node through a first transmission line. The node is connected to the first and second signal receiving terminals through second and third transmission lines. The second transmission line is longer than the third transmission line, and a difference between lengths of the second and third transmission lines is greater than a product of a transmission speed and a rise time of signals from the driving terminal. A first terminal of the capacitor is connected to the third transmission line. A second terminal of the capacitor is grounded. A distance between the capacitor and the second signal receiving terminal is less than a distance between the capacitor and the node.

Abstract: A printed circuit board includes a signal layer and a reference layer. The signal layer is covered with copper foil. A circuit topology for multiple loads is set on the signal layer. The circuit topology includes a driving terminal, a first signal receiving terminal, and a second signal receiving terminal. The driving terminal is connected to a node through a first transmission line. The node is connected to the first and second signal receiving terminals respectively through a second and a third transmission lines. A difference between lengths of the second and third transmission lines is greater than a product of a transmission speed and a rise time of signals from the driving terminal. The reference layer is covered with copper foil, and arranged under the signal layer. A region without copper foil is formed on the reference layer, under the second transmission line.

Abstract: A printed circuit board (PCB) includes two layers, two signal transmission traces, and a vertical interconnect access (via). The signal transmission traces are respectively arranged on the layers. The signal transmission traces are electrically connected to each other through the via. A centerline of the via with a vertical line of the layers form an acute angle ?, the angle ? is less than cos?1[(Lv2?Lt2)/(Lv2+Lt2)]. Wherein Lt is loss of the two signal transmitting traces in a unit length, and Lv is loss of the via in a unit length.

Abstract: In a method for checking layout of a printed circuit board (PCB) using an electronic device, a signal line is selected from a layout diagram of the PCB. The method searches for signal lines which have an acute angle when deviating from a straight line in the layout diagram of the PCB. The method further locates attribute data of the searched signal lines in the layout diagram of the PCB, and displays the attribute data of the searched signal lines on a display device of the electronic device.

Abstract: A computing device and a method reads design standards of signal transmission lines in a printed circuit board (PCB) layout file, and determines a minimum reference length of line segments of the signal transmission lines from the design standards. The device and method then selects a signal transmission line from a circuit board, and computes an actual length of each line segment of the selected signal transmission line. If each actual length is more than or equal to the minimum reference length, the device and method determines length design of the selected signal transmission line satisfies the design standards. Otherwise, if any actual length is less than the minimum reference length, the device and method determines the length design of the signal transmission line does not satisfy the design standards.

Abstract: A pad includes a first mating section and a second mating section. The first mating section includes a first horizontal plane and a first inclined plane. The second mating section includes a second horizontal plane and a second inclined plane. The first mating section is a copper foil capable of being connected to a wire. The second mating section is made of insulating material. The first inclined plane and the second inclined plane are bonded together.

Abstract: A circuit board includes a current balancing unit that receives a number of current values from ammeters. A minimum current value between the current values is determined by the current balancing unit. Resistance of one or more variable resistors of the current balancing unit is adjusted by the current balancing unit to make the current value from one or more the ammeters serially connected to the one or more the variable resistors to be substantially equal to the minimum current value.

Abstract: A printed circuit board (PCB) includes a top signal layer, a bottom signal layer, a ground layer, a plurality of vias, and at least two ground vias. Both the top signal layer and the bottom signal layer include at least one protection line. The ground layer is located between the top signal layer and the bottom signal layer. The at least two ground vias extend through the PCB and are located adjacent to the vias on the PCB. The at least two ground vias are electrically connected to the ground layer to conduct noise signals, and the at least two ground vias are electrically connected by the protection lines to insulate noise signals.

Abstract: A motherboard interconnection method includes positioning a first and a third electronic elements on a top layer of a motherboard interconnection device, and positioning a second and a fourth electronic elements on a bottom layer of the motherboard interconnection device. The method connects a first end of the first electronic element on the top layer to the first end of the second electronic element on the bottom layer with a first via hole, and connects the first end of the third electronic element on the top layer to the first end of the fourth electronic element on the bottom layer with a second via hole. The method further connects a second ends of the two electronic elements on the top layer to a first part, and connects the second ends of the two electronic elements on the bottom layer to a second part.

Abstract: A circuit board includes a substrate and a copper layer positioned on the substrate. The copper layer includes a BGA area and a non-BGA area, and includes traces. The widths of the traces in the BGA area are smaller than the widths of the traces in the non-BGA area, the dielectric coefficient of the substrate in the BGA area is greater than the dielectric coefficient of the substrate in the non-BGA area for keeping the impedance of the traces consistent in the BGA area and in the non-BGA area.