Abstract: A motherboard layout method includes positioning two electronic elements on a top layer of a motherboard, and positioning another two electronic elements on a bottom layer of the motherboard, connecting one end of a first electronic element on the top layer to the same end of a first electronic element on the bottom layer with a first via hole, and connecting the same end of a second electronic element on the top layer to the same end of a second electronic element on the bottom layer with a second via hole. The method further includes connecting the other ends of the two electronic elements on the top layer to a first part, and connecting the other ends of the two electronic elements on the bottom layer to a second part.

Abstract: A method for removing a stub of a via hole includes copperizing a wall of a via hole in a top layer of a printed circuit board (PCB) if signal lines are located on the top layer of the PCB, and a wall of the via hole in a bottom layer of the PCB is not copperized. The method further includes connecting the top layer and the bottom layer of the PCB using a connection layer.

Abstract: A flexible printed circuit board (FPCB) includes a signal layer, upper and lower ground layers, and two dielectric layers. The signal layer includes a differential pair comprising two transmission lines to transmit a pair of differential signals. The dielectric layers are located on and under the signal layer to sandwich the signal layer. The upper ground layer is attached to the dielectric layer on the signal layer, opposite to the signal layer. The lower ground layer is attached to the dielectric layer under the signal layer, opposite to the signal layer. Each ground layer includes a grounded sheet made of conductive material. Two voids are defined in each ground layer and located at opposite sides of the corresponding grounded sheet. Distances between the middle line of the grounded sheet of each ground layer and middle lines of the two transmission lines are equal.

Abstract: A flexible printed circuit board (FPCB) includes a signal layer comprising a differential pair, a ground layer comprising a grounded sheet made of conductive material, and a dielectric layer located between the signal layer and the ground layer. A void is located on the two opposite sides of the grounded sheet in the ground layer. The differential pair comprises two transmission lines and each transmission line is capable of transmitting a differential signal. The distances between the middle line of the grounded sheet and the middle line of each of the two transmission lines are equal.

Abstract: An exemplary PCB includes a first reference layer, a first signal layer, a second signal layer, and a third signal layer in that order, a first differential pair is arranged in the first signal layer in edge-coupled structure and references the first reference layer, a distance between the first signal layer and the second signal layer is greater than a distance between the first reference layer and the first signal layer, a second differential pair is arranged in the second signal layer and the third signal layer in broad-coupled structure. The PCB has a high density layout of transmission lines.

Abstract: A system for analyzing lengths of branches of signal paths is disclosed. The system includes: a signal path naming module for naming all signal paths of a PCB; a signal path group selecting module for selecting a group of signal paths to be analyzed from the database; a signal path selecting module for selecting signal paths to be analyzed from the group of signal paths; a branch searching module for analyzing the selected signal paths, to search passive circuit components and external circuits connected to the selected signal paths for corresponding branches of the selected signal paths; a branch length calculating module for calculating a length of each branch; and a branch length comparing module for comparing each calculated branch length with a corresponding predefined maximal branch length to determine whether the calculated branch length is more than the predefined maximal branch length. A related method is also disclosed.

Abstract: A circuit topology for multiple loads is provided. In an embodiment, the circuit topology includes a driving terminal (50), a first node (A), a first receiving terminal (10), and a second receiving terminal (20). The driving terminal is coupled to the first node via a main transmission line (11), the first node is respectively coupled to the first and second receiving terminals via a first branch transmission line (13) and a second branch transmission line (12). A first resistor (R2) is mounted on the second branch transmission line, a distance the signal travels from the driving terminal to the second receiving terminal via the main transmission line and the second branch transmission line is greater than a distance the signal travels from the driving terminal to the first receiving terminal via the main transmission and the first branch transmission line.

Abstract: A system for analyzing lengths of branches of signal paths is disclosed. The system includes: a signal path naming module for naming all signal paths of a PCB; a signal path group selecting module for selecting a group of signal paths to be analyzed from the database; a signal path selecting module for selecting signal paths to be analyzed from the group of signal paths; a branch searching module for analyzing the selected signal paths, to search passive circuit components and external circuits connected to the selected signal paths for corresponding branches of the selected signal paths; a branch length calculating module for calculating a length of each branch; and a branch length comparing module for comparing each calculated branch length with a corresponding predefined maximal branch length to determine whether the calculated branch length is more than the predefined maximal branch length. A related method is also disclosed.