Patents by Inventor Chia-Pin Chiu

Chia-Pin Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12191220
    Abstract: Embodiments include semiconductor packages. A semiconductor package includes a hybrid interposer with a first region and a second region. The first region is comprised of glass or low thermal conductive materials, and the second region is comprised of silicon or diamond materials. The semiconductor package includes a first die on the first region of the hybrid interposer, a second die on the second region of the hybrid interposer, and an integrated heat spreader over the first die, the second die, and the hybrid interposer. The hybrid interposer includes first and second interconnects, where the first interconnects vertically extend from a bottom surface of the first region to a top surface of the first region, and where the second interconnects vertically extend from a bottom surface of the second region to a top surface of the second region. The first interconnects are through-glass vias, and the second interconnects are through-silicon vias.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: January 7, 2025
    Assignee: Intel Corporation
    Inventors: Zhimin Wan, Chandra Mohan Jha, Je-Young Chang, Chia-Pin Chiu
  • Publication number: 20250004206
    Abstract: In one embodiment, an integrated circuit package includes a first (top) package substrate, a photonics integrated circuit (PIC) die coupled to the first package substrate, and a second package substrate coupled to a bottom side of the first package substrate. The package further includes a pedestal coupled to a top side of the second package substrate in an area of the second package substrate that extends beyond an edge of the first package substrate at which the PIC die is located.
    Type: Application
    Filed: June 28, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Chia-Pin Chiu, Tim T. Hoang, Kaveh Hosseini, Omkar G. Karhade
  • Publication number: 20240429173
    Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
    Type: Application
    Filed: September 3, 2024
    Publication date: December 26, 2024
    Inventors: Henning BRAUNISCH, Chia-Pin CHIU, Aleksandar ALEKSOV, Hinmeng AU, Stefanie M. LOTZ, Johanna M. SWAN, Sujit SHARAN
  • Patent number: 12176676
    Abstract: Embodiments disclosed herein include dual sided cooling architectures for laser packages. In an embodiment, an electronic package comprises a package substrate, and a laser chip attached to the package substrate. In an embodiment, the laser chip has a first surface and a second surface opposite from the first surface. In an embodiment, an interposer is disposed over the laser chip, where the interposer overhangs an edge of the laser chip. In an embodiment, the electronic package further comprises an interconnect between the interposer and the package substrate.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: December 24, 2024
    Assignee: Intel Corporation
    Inventor: Chia-Pin Chiu
  • Publication number: 20240421073
    Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.
    Type: Application
    Filed: August 28, 2024
    Publication date: December 19, 2024
    Inventors: Robert STARKSTON, Debendra MALLIK, John S. GUZEK, Chia-Pin CHIU, Deepak KULKARNI, Ravi V. MAHAJAN
  • Publication number: 20240402442
    Abstract: The substrate of an integrated circuit component comprises a cutout that extends fully or partially through the substrate. An edge of a photonic integrated circuit (PIC) in the integrated circuit component is coplanar with a wall of the cutout or extends into the cutout. An optical fiber in an FAU is aligned with a waveguide within the PIC and the FAU is attached to the PIC edge and an attachment block. The attachment block provides an increased attachment surface area for the FAU. A portion of the FAU extends into the substrate cutout. A stress relief mechanism can secure the fiber optic cable attached to the FAU to the substrate to at least partially isolate the FAU-PIC attachment from external mechanical forces applied to the optical fiber cable. The integrated circuit component can be attached to a socket that comprises a socket cutout into which an FAU can extend.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 5, 2024
    Applicant: Intel Corporation
    Inventors: Chia-Pin Chiu, Xiaoqian Li, Kaveh Hosseini, Tim T. Hoang
  • Publication number: 20240339428
    Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.
    Type: Application
    Filed: June 20, 2024
    Publication date: October 10, 2024
    Inventors: Weng Hong TEH, Chia-Pin CHIU
  • Patent number: 12113026
    Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
    Type: Grant
    Filed: October 9, 2023
    Date of Patent: October 8, 2024
    Assignee: Intel Corporation
    Inventors: Henning Braunisch, Chia-Pin Chiu, Aleksandar Aleksov, Hinmeng Au, Stefanie M. Lotz, Johanna M. Swan, Sujit Sharan
  • Publication number: 20240329301
    Abstract: A substrate for a multi-chip package includes at least one photonic integrated circuit (PIC) interposer mounted in a cavity in a first major surface. Each PIC interposer is configured to electrically connect with, or optically couple to, a plurality of integrated circuit devices. The substrate further includes at least one optical coupler that is optically coupled to the PIC interposer.
    Type: Application
    Filed: April 3, 2023
    Publication date: October 3, 2024
    Inventors: Kaveh Hosseini, Ravindranath V. Mahajan, Chia-Pin Chiu
  • Publication number: 20240329313
    Abstract: Technologies for optical coupling to photonic integrated circuit (PIC) dies are disclosed. In one illustrative embodiment, a PIC die has one or more waveguides. A lens array is positioned adjacent the PIC die. Light from waveguides of the PIC die reflects off of a reflective surface of the lens array. The reflective surface directs the light from the PIC die towards lenses in the lens array. The lenses collimate the light, facilitating coupling of light to and from other components. The reflective surface on the lens array may be oriented at any suitable angle, resulting in a collimated beam of light that is oriented at any suitable angle.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Applicant: Intel Corporation
    Inventors: Chia-Pin Chiu, Kaveh Hosseini, Xiaoqian Li
  • Patent number: 12107042
    Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.
    Type: Grant
    Filed: October 24, 2022
    Date of Patent: October 1, 2024
    Assignee: Intel Corporation
    Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan
  • Publication number: 20240319457
    Abstract: In one embodiment, a photonic integrated circuit (PIC) device includes conductive pads on a surface of the PIC and a micro ring resonator (MRR) with a heater element centrally located between the conductive pads. The PIC also includes a cavity defined within a substrate of the PIC below the MRR, and a plurality of holes defined between the MRR and the conductive pads. The holes extend from a top surface of the PIC into the cavity, and each hole is between a respective conductive pad and the MRR.
    Type: Application
    Filed: March 24, 2023
    Publication date: September 26, 2024
    Applicant: Intel Corporation
    Inventors: Chia-Pin Chiu, Kaveh Hosseini
  • Publication number: 20240319437
    Abstract: A photonic integrated circuit (PIC), a semiconductor assembly including the PIC, a multi-chip package including the PIC, and a method of forming the PIC. The PIC includes a PIC substrate, and a semiconductor layer on a top surface of the PIC substrate and including a semiconductor material and an optical component. The PIC substrate defines an air cavity therein extending in a direction from a bottom surface of the PIC substrate toward and in registration with the optical component. The semiconductor layer is free of any opening therethrough in communication with the air cavity.
    Type: Application
    Filed: March 24, 2023
    Publication date: September 26, 2024
    Applicant: Intel Corporation
    Inventors: Xiaoqian Li, Omkar G. Karhade, Nitin A. Deshpande, Julia Chiu, Chia-Pin Chiu, Kaveh Hosseini, Madhubanti Chatterjee
  • Patent number: 12099245
    Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, where the package substrate comprises a recessed edge. In an embodiment, a compute die is on the package substrate, and an optics die on the package substrate and overhanging the recessed edge of the package substrate. In an embodiment, an integrated heat spreader (IHS) is over the compute die and the optics die. In an embodiment, a lid covers the recess in the package substrate.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: September 24, 2024
    Assignee: Intel Corporation
    Inventors: Asako Toda, Chia-Pin Chiu, Xiaoqian Li, Yiqun Bai
  • Patent number: 12094800
    Abstract: Embodiments include semiconductor packages. A semiconductor package includes first and second bottom dies on a package substrate, first top dies on the first bottom die, and second top dies on the second bottom die. The semiconductor package includes thermally conductive slugs on the first bottom die and the second bottom die. The thermally conductive slugs are comprised of a high thermal conductive material. The thermally conductive slugs are positioned directly on outer edges of top surfaces of the first and second bottom dies, inner edges of the top surfaces of the first and second bottom dies, and/or a top surface of the package substrate. The high thermal conductive material of the thermally conductive slugs is comprised of copper, silver, boron nitride, or graphene. The thermally conductive slugs may have two different thicknesses. The semiconductor package may include an active die and/or an integrated heat spreader with the pedestals.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: September 17, 2024
    Assignee: Intel Corporation
    Inventors: Zhimin Wan, Jin Yang, Chia-Pin Chiu, Peng Li, Deepak Goyal
  • Patent number: 12051667
    Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.
    Type: Grant
    Filed: September 27, 2023
    Date of Patent: July 30, 2024
    Assignee: Intel Corporation
    Inventors: Weng Hong Teh, Chia-Pin Chiu
  • Patent number: 12009321
    Abstract: In various aspects, a package system includes at least a first package and a second package arranged on a same side of the package carrier. Each of the first package and the second package comprises an antenna to transmit and/or receive radio frequency signals. A cover may be arranged at a distance over the first package and the second package at the same side of the package carrier as the first package and the second package. The cover comprises at least one conductive element forming a predefined pattern on a side of the cover facing the first package and the second package. The predefined pattern is configured as a frequency selective surface. The package system further includes a radio frequency signal interface wirelessly connecting the antennas of the first package and the second package. The radio frequency signal interface comprises the at least one conductive element.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: June 11, 2024
    Assignee: Intel Corporation
    Inventors: Zhen Zhou, Tae Young Yang, Tolga Acikalin, Johanny Escobar Pelaez, Kenneth P. Foust, Chia-Pin Chiu, Renzhi Liu, Cheng-Yuan Chin
  • Patent number: 11984396
    Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: May 14, 2024
    Assignee: Intel Corporation
    Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan
  • Publication number: 20240061192
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, the electronic package comprises a package substrate, a die coupled to the package substrate, a photonics integrated circuit (PIC) coupled to the die, and a fiber array unit (FAU) optically coupled to the PIC. In an embodiment, the FAU has a base with a first width and a protrusion with a second width that is smaller than the first width.
    Type: Application
    Filed: August 16, 2022
    Publication date: February 22, 2024
    Inventors: Chia-Pin CHIU, Finian ROGERS, Tim Tri HOANG, Kaveh HOSSEINI, Omkar KARHADE
  • Publication number: 20240038671
    Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
    Type: Application
    Filed: October 9, 2023
    Publication date: February 1, 2024
    Inventors: Henning BRAUNISCH, Chia-Pin CHIU, Aleksandar ALEKSOV, Hinmeng AU, Stefanie M. LOTZ, Johanna M. SWAN, Sujit SHARAN