Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a fin base disposed on the substrate, nanostructured channel regions disposed on a first portion of the fin base, a gate structure surrounding the nanostructured channel regions, a source/drain (S/D) region disposed on a second portion of the fin base, and an isolation structure disposed between the S/D region and the second portion of the fin base. The isolation structure includes an undoped semiconductor layer disposed on the second portion of the fin base, a silicon-rich dielectric layer disposed on the undoped semiconductor layer, and an air spacer disposed on the silicon-rich dielectric layer.

Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, the electronic package comprises a package substrate, a die coupled to the package substrate, a photonics integrated circuit (PIC) coupled to the die, and a fiber array unit (FAU) optically coupled to the PIC. In an embodiment, the FAU has a base with a first width and a protrusion with a second width that is smaller than the first width.

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

Abstract: In various aspects, a device-to-device communication system is provided including a first device and a second device. Each of the first device and the second device includes an antenna, a radio frequency frond-end circuit, and a baseband circuit. Each of the first device and the second device are at least one of a chiplet or a package. The device-to-device communication system further includes a cover structure housing the first device and the second device. Each of the first device and the second device are at least one of a chiplet or a package. The device-to-device communication system further includes a radio frequency signal interface wirelessly communicatively coupling the first device and the second device. The radio frequency signal interface includes the first antenna and the second antenna.

Abstract: Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first and second bottom dies on a package substrate. The semiconductor package includes first top dies on the first bottom die, second top dies on the second bottom die, and a pedestal on the first and second bottom dies. The pedestal comprises a high thermal conductive material and is positioned on a region of top surfaces of the first and second bottom dies. The semiconductor package includes an encapsulation layer over the first and second bottom dies, and surrounds the first and second top dies and the pedestal. The semiconductor package includes a TIM over the first and second top dies, pedestal, and encapsulation layer, and an integrated heat spreader (IHS) over the TIM. The pedestal is on a periphery region of the top surfaces of the first and second bottom dies.

Abstract: In one embodiment, an integrated circuit package includes a package substrate with a cavity, an integrated circuit device, a bridge, a photonic integrated circuit (PIC), and an electronic integrated circuit (EIC). The integrated circuit device is electrically coupled to the package substrate. The bridge and the PIC are in the cavity of the package substrate, and the bridge is electrically coupled to the package substrate. The EIC is above, and electrically coupled to, the bridge and the PIC.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises an interposer, a first die attached to the interposer, and a second die attached to the interposer. In an embodiment, the electronic package further comprises a heatsink thermally coupled to the first die and the second die. In an embodiment, the heatsink has a first surface facing away from the first die and the second die and a second surface facing the first die and the second die. In an embodiment, the heatsink comprises a thermal break between the first die and the second die.

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

Abstract: Embodiments of a microelectronic assembly comprise a package substrate, a first integrated circuit (IC) die, a second IC die between the first IC die and the package substrate, a dielectric material between the first IC die and the package substrate, and a plurality of vias through the dielectric material, the vias coupling the first IC die and the package substrate. The microelectronic assembly is in a space defined by three mutually orthogonal axes, a first axis, a second axis and a third axis; the package substrate, the first IC die and the second IC die are mutually parallel in first planes defined by the first axis and the third axis; the vias are in one or more second planes defined by the second axis and the third axis; and the vias are inclined at an angle not equal to ninety degrees around the first axis.

Abstract: A reduced bridge structure for a photonic integrated circuit (PIC) or any integrated circuit comprising a ring resonator structure. The reduced bridge structure is an architecture including an optical and electrical routing arrangement to reduce the number of bridges around the micro-ring structure of the ring resonator structure. Embodiments reserve one bridge portion for use as a signal trace, not routing the signal trace over a silicon waveguide. By not routing the signal trace over a silicon waveguide, the structure avoids possible interference between the radio frequency (RF) signal on the signal trace and optical communication (a light wave) propagating in the silicon waveguide.

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

Abstract: Variations in a thermal structure for an open cavity photonic integrated circuit (OCPIC) having an MRR. The structure includes an air trench in fluid communication with an air cavity that is located under the MRR. The air trench is a gap/opening in the oxide that encircles at least a portion of the MRR and extends outward radially therefrom, with a consistent width, to a diameter D1. An oxide cladding is not removed in areas that are used for metal traces and routing. The structure is characterized by straight walls along the air trench. The structure has a lower diameter D2, measured at a bottom/floor of the air cavity. In various embodiments, D2 is substantially equal to D1.

Abstract: Covered cavity structure for Photonic integrated circuits (PICs) that include a micro-ring resonator (MRR) with a heater. Air cavities are etched or otherwise thinned into an overlaying oxide layer, a buried oxide layer, or an underlying silicon layer. Variations in size, shape, and location of the covered air cavity associated with an MRR provide customizable options for thermal management. A thin film across an upper surface covers the air cavity, providing a barrier to underfill in the air cavity and preventing interference of underfill with performance of silicon waveguides. When arrayed into a plurality of MRRs, the thin film can cover the plurality of MRRs.

Abstract: Embodiments disclosed herein include an on-cavity photonic integrated circuit (OCPIC). In an embodiment, the OCPIC comprises a laser transmitter, that comprises a row with four bumps, and a micro-ring resonator (MRR) in the row between a first bump and a second bump of the four bumps. In an embodiment, a cavity is below the MRR, where a diameter of the cavity is substantially equal to a spacing between the first bump and the second bump.

Abstract: Embodiments disclosed herein include an optoelectronic system. In an embodiment, the optoelectronic system comprises a first substrate, a second substrate over the first substrate, and a micro-ring resonator (MRR) over the second substrate. In an embodiment, a heater is integrated into the MRR, a cladding is over the MRR, and a temperature sensor is over the MRR in the cladding.

Abstract: Embodiments disclosed herein include optoelectronic systems and methods of forming such systems. In an embodiment, an optoelectronic system comprises a first substrate, a second substrate over the first substrate, a micro-ring resonator (MRR) over the second substrate, a heater integrated into the MRR, a cladding over the MRR, an opening through the first substrate and the second substrate to expose a bottom surface of the MRR, and a base spanning across the opening.

Abstract: Embodiments disclosed herein include optoelectronic systems and methods of forming such systems. In an embodiment, an optoelectronic system comprises a first substrate, a second substrate over the first substrate, and a micro-ring resonator (MRR) over the second substrate. In an embodiment, a heater is integrated into the MRR, a cladding is over the MRR, and an opening is through the first substrate and the second substrate to expose a bottom surface of the MRR.