Patents by Inventor Chia-Pin Chiu

Chia-Pin Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE
    Publication number: 20190393180
    Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BRIM substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.
    Type: Application
    Filed: September 5, 2019
    Publication date: December 26, 2019
    Inventors: Weng Hong Teh, Chia-Pin Chiu
  • Multi-chip package and method of providing die-to-die interconnects in same
    Patent number: 10510669
    Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: December 17, 2019
    Assignee: Intel Corporation
    Inventors: Henning Braunisch, Chia-Pin Chiu, Aleksandar Aleksov, Hinmeng Au, Stefanie M. Lotz, Johanna M. Swan, Sujit Sharan
  • High density substrate routing in package
    Patent number: 10438915
    Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Weng Hong Teh, Chia-Pin Chiu
  • PRINTED CIRCUIT BOARD ASSEMBLY
    Publication number: 20190297724
    Abstract: Printed circuit board assembly (PCBA) technology is disclosed. A PCBA can include a printed circuit board (PCB). The PCBA can also include a capacitor operably mounted on a side of the PCB. In addition, the PCBA can include a damper material coupled to the PCB and operable to dissipate kinetic energy generated by the capacitor during operation. An electronic system including a capacitor and damping material, and a method for minimizing acoustic vibration in an electronic system are also disclosed.
    Type: Application
    Filed: March 20, 2018
    Publication date: September 26, 2019
    Applicant: Intel Corporation
    Inventor: Chia-Pin Chiu
  • Localized high density substrate routing
    Patent number: 10366951
    Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: July 30, 2019
    Assignee: Intel Corporation
    Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravindranath V. Mahajan
  • Heat sink for 5G massive antenna array and methods of assembling same
    Patent number: 10320051
    Abstract: A massive array antenna apparatus is configured with a cantilevered heat pipe that allows a semiconductive millimeter-wave device to move independently from a heat-sink base during thermal expansion and contraction.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventor: Chia-Pin Chiu
  • HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE
    Publication number: 20190139926
    Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.
    Type: Application
    Filed: January 4, 2019
    Publication date: May 9, 2019
    Inventors: Weng Hong Teh, Chia-Pin Chiu
  • Multi-chip-module semiconductor chip package having dense package wiring
    Patent number: 10256211
    Abstract: An apparatus is described having a build-up layer. The build-up layer has a pad side of multiple die pressed into a bottom side of the build-up layer. The multiple die have wide pads to facilitate on wafer testing of the multiple die. The wide pads are spaced a minimum distance permitted by a manufacturing process used to manufacture their respective die. The build-up layer above the wide pads is removed. The apparatus also includes metallization on a top side of the build-up layer that substantially fills regions above the wide pads. The metallization includes lands above the wide pads and multiple wires between the wide pads.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: April 9, 2019
    Assignee: Intel Corporation
    Inventors: Chuan Hu, Chia-Pin Chiu, Johanna Swan
  • High density substrate routing in package
    Patent number: 10199346
    Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: February 5, 2019
    Assignee: Intel Corporation
    Inventors: Weng Hong Teh, Chia-Pin Chiu
  • HEAT SINK FOR 5G MASSIVE ANTENNA ARRAY AND METHODS OF ASSEMBLING SAME
    Publication number: 20190006731
    Abstract: A massive array antenna apparatus is configured with a cantilevered heat pipe that allows a semiconductive millimeter-wave device to move independently from a heat-sink base during thermal expansion and contraction.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 3, 2019
    Inventor: Chia-Pin Chiu
  • STACKED-DIE INCLUDING A DIE IN A PACKAGE SUBSTRATE
    Publication number: 20180366444
    Abstract: Some embodiments described herein include apparatuses and methods of forming such apparatuses. In one such embodiment, an apparatus may include a substrate, a first die, and a second die coupled to the first die and the substrate. The substrate may include an opening. At least a portion of the die may occupy at least a portion of the opening in the substrate. Other embodiments including additional apparatuses and methods are described.
    Type: Application
    Filed: May 11, 2018
    Publication date: December 20, 2018
    Inventor: Chia-Pin Chiu
  • LOCALIZED HIGH DENSITY SUBSTRATE ROUTING
    Publication number: 20180350737
    Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.
    Type: Application
    Filed: June 7, 2018
    Publication date: December 6, 2018
    Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravindranath V. Mahajan
  • Enhanced fiducial visibility and recognition
    Patent number: 10049987
    Abstract: Particular embodiments described herein provide for a base, a plurality of fiducials on the base, and a fluid in one or more of each of the plurality of fiducials to increase recognition of each of the one or more fiducials that includes the fluid by one or more pattern recognition devices. In an example, the fluid is an epoxy and the fiducials are used to determine a placement of components in a component space.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: August 14, 2018
    Assignee: Intel Corporation
    Inventors: Chia-Pin Chiu, Kyle Yazzie
  • ENHANCED FIDUCIAL VISIBILITY AND RECOGNITION
    Publication number: 20180182712
    Abstract: Particular embodiments described herein provide for a base, a plurality of fiducials on the base, and a fluid in one or more of each of the plurality of fiducials to increase recognition of each of the one or more fiducials that includes the fluid by one or more pattern recognition devices. In an example, the fluid is an epoxy and the fiducials are used to determine a placement of components in a component space.
    Type: Application
    Filed: December 27, 2016
    Publication date: June 28, 2018
    Applicant: Intel Corporation
    Inventors: Chia-Pin Chiu, Kyle Yazzie
  • Bridge interconnect with air gap in package assembly
    Patent number: 10008451
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: June 26, 2018
    Assignee: Intel Corporation
    Inventors: Chia-Pin Chiu, Zhiguo Qian, Mathew J. Manusharow
  • Stacked-die including a die in a package substrate
    Patent number: 10008475
    Abstract: Some embodiments described herein include apparatuses and methods of forming such apparatuses. In one such embodiment, an apparatus may include a substrate, a first die, and a second die coupled to the first die and the substrate. The substrate may include an opening. At least a portion of the die may occupy at least a portion of the opening in the substrate. Other embodiments including additional apparatuses and methods are described.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: June 26, 2018
    Assignee: Intel Corporation
    Inventor: Chia-Pin Chiu
  • HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE
    Publication number: 20180145047
    Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.
    Type: Application
    Filed: January 17, 2018
    Publication date: May 24, 2018
    Inventors: Weng Hong Teh, Chia-Pin Chiu
  • MULTI-CHIP PACKAGE AND METHOD OF PROVIDING DIE-TO-DIE INTERCONNECTS IN SAME
    Publication number: 20180145031
    Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
    Type: Application
    Filed: January 19, 2018
    Publication date: May 24, 2018
    Inventors: Henning BRAUNISCH, Chia-Pin CHIU, Aleksandar ALEKSOV, Hinmeng AU, Stefanie M. LOTZ, Johanna M. SWAN, Sujit SHARAN
  • Package on Package Structure Having Package To Package Interconnect Composed of Packed Wires Having A Polygon Cross Section
    Publication number: 20180090471
    Abstract: An apparatus is described that includes a package on package structure. The package on package structure includes an interposer to implement electrical interconnections between an upper package of the package on package structure and a lower package of the package on package structure. The interposer has packed wires, the packed wires have respective polygonal cross sections.
    Type: Application
    Filed: September 28, 2016
    Publication date: March 29, 2018
    Inventors: Chia-Pin CHIU, Yoshihiro TOMITA, Yoko SEKIHARA, Robert L. SANKMAN
  • High density substrate routing in BBUL package
    Patent number: 9929119
    Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: March 27, 2018
    Assignee: Intel Corporation
    Inventors: Weng Hong Teh, Chia-Pin Chiu