Abstract: An internal rotor type nail drive device of electric nail gun, comprising a nailing rod and an internal rotor type rotary actuator that can output a specific rotation angle and can drive the nailing rod to move downward for nailing. Specifically, the rotary actuator comprises a stator and a rotor arranged inside the stator, even groups of electromagnetic mutual action components are configured in pairs between the stator and the rotor, to generate a tangential force to drive the rotor to rotate for a specific rotation angle, and to drive the nailing rod to move for a nailing stroke. The nailing stroke can be determined by a specific rotation angle. Thus, through the above configuration of the rotary actuator, the structure of the electric nail gun can be simplified, and the kinetic energy for nailing can be increased.

Abstract: A method of estimating greenhouse gas emission, performed by a processing device, includes: obtaining at least one time period of a number of working stations for a target manufacturing process of a product; obtaining a number of first power consumption data of the target manufacturing process, wherein the first power consumption data correspond to the working stations respectively; calculating a number of second power consumption data based on the at least one time period and the first power consumption data; searching for a number of target coefficients corresponding to the plurality of working stations respectively in coefficient database based on the target manufacturing process; and calculating greenhouse gas emission data of the target manufacturing process based on the second power consumption data and the target coefficients.

Abstract: A package structure includes a first die and a second die embedded in a first molding material, a first redistribution structure over the first die and the second die, a second molding material over portions of the first die and the second die, wherein the second molding material is disposed between a first portion of the first redistribution structure and a second portion of the first redistribution structure, a first via extending through the second molding material, wherein the first via is electrically connected to the first die, a second via extending through the second molding material, wherein the second via is electrically connected to the second die and a silicon bridge electrically coupled to the first via and the second via.

Abstract: An optoelectronic device includes a photonic component. The photonic component includes an active side, a second side different from the active side, and an optical channel extending from the active side to the second side of the photonic component. The optical channel includes a non-gaseous material configured to transmit light.

Abstract: A chip package including a substrate, a first conductive structure, and an electrical isolation structure is provided. The substrate has a first surface and a second surface opposite the first surface), and includes a first opening and a second opening surrounding the first opening. The substrate includes a sensor device adjacent to the first surface. A first conductive structure includes a first conductive portion in the first opening of the substrate, and a second conductive portion over the second surface of the substrate. An electrical isolation structure includes a first isolation portion in the second opening of the substrate, and a second isolation portion extending from the first isolation portion and between the second surface of the substrate and the second conductive portion. The first isolation portion surrounds the first conductive portion.

Abstract: A method for manufacturing a golf ball having a multi-layered pattern is provided. Firstly, a semi-finished product of the golf ball is provided and includes a ball-shaped body and a base layer covering an outer surface of the ball-shaped body. Then, the semi-finished product of the golf ball is rotated at a predetermined rotation speed, and a color paint is applied to the semi-finished product of the golf ball by spraying from each of an upper position, a middle position, and a lower position. The multi-layered pattern includes an upper-layer pattern area, a mid-layer pattern area, and a lower-layer pattern area that are different in color from each other.

Abstract: A method of making a ROM structure includes the operations of forming an active area having a channel, a source region, and a drain region; depositing a gate electrode over the channel; depositing a conductive line over at least one of the source region and the drain region; adding dopants to the source region and the drain region of the active area; forming contacts to the gate electrode, the source region, and the drain; depositing a power rail, a bit line, and at least one word line of the integrated circuit against the contacts; and dividing the active area with a trench isolation structure to electrically isolate the gate electrode from the source region and the drain region.

Abstract: Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.

Abstract: A method of reducing gray energy consumption and achieving optimal gray energy saving for carbon neutralization is proposed. In a cellular network, each cell or BS (group of cells) has renewable (green) and non-renewable (gray, on-grid power) energy sources. The renewable (green) energy is highly variable and unpredictable, while non-renewable (gray, on-grid power) is stable but is not renewable and thus has more carbon impact. Each cell or BS (group of cells) services is associated UEs when it is on. In one novel aspect, a cell or BS (group of cells) that consumes more non-renewable energy can give some or all of its served UEs to another cell or BS (group of cells) that consumes less non-renewable energy.

Abstract: A method includes forming a dummy pattern over test region of a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the dummy pattern; removing the dummy pattern to form an opening; forming a dielectric layer in the opening; performing a first testing process on the dielectric layer; performing an annealing process to the dielectric layer; and performing a second testing process on the annealed dielectric layer.

Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.

Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.

Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: A lock is provided, including: a housing; a latch member, movably mounted to the housing and including a first blocking portion; a blocking member, movably mounted to the housing and including a second blocking portion; a locking member, operably mounted to the housing; wherein when the locking member is in a locking state and the latch member is in a first position, the locking member and the blocking member are free of blocking from each other so that the first blocking portion and the second blocking portion are blocked with each other, and the latch member is unmovable toward a second position; when the locking member is in a unlocked state, the second blocking portion and the first blocking portion are unblocked with each other and the latch member is movable to the second position so that the latch member is retractable from a locked object.

Abstract: A method includes forming first IC devices on a first frontside of a first semiconductor substrate and second IC devices on a second frontside of a second semiconductor substrate; forming a first contact pad over the first IC devices from the first frontside and a second contact pad over the second IC device from the second frontside; bonding the first and second contact pads such that the first and second IC devices are electrically connected; and forming a conductive structure on a first backside of the first semiconductor substrate. The conductive structure includes a through via (TV), a backside metal (BSM) feature, and a backside redistribution layer (BRDL). The TV is extending through the first semiconductor substrate and electrically connected the first and second IC devices to the BRDL, and the BSM feature is extended into a portion of the first semiconductor substrate and electrically connected to the TV.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.