Abstract: A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 ?m to 750 ?m, and the wall surface of the dam element surrounding the sensing area is a rough surface.

Abstract: This present invention provides a method of manufacturing a chip scale sensing chip package, comprising the steps of: providing a sensing device wafer having a first top surface and a first bottom surface opposite to each other, whereby the sensing device wafer comprises a plurality of chip areas, and each of the chip areas comprising a sensing device and a plurality of conductive pads adjacent to the sensing chip nearby the first top surface; providing a cap wafer having a second top surface and a second bottom surface opposite to each other, and bonding the second surface of the cap wafer to the first top surface of the sensing device wafer by sandwiching a first adhesive layer therebetween; providing a temporary carrier substrate, and bonding the temporary carrier substrate to the second top surface of the cap wafer by sandwiching a second adhesive layer therebetween; forming a wiring layer connecting to each of the conductive pads on the first bottom surface of the sensing device wafer; providing a first

Abstract: A method of manufacturing chip package includes providing a semiconductor substrate having at least a photo diode and an interconnection layer. The interconnection layer is disposed on an upper surface of the semiconductor substrate and above the photo diode and electrically connected to the photo diode. At least a redistribution circuit is formed on the interconnection layer. The redistribution circuit is electrically connected to the interconnection layer. A packaging layer is formed on the redistribution circuit. Subsequently, a carrier substrate is attached to the packaging layer. A color filter is formed on a lower surface of the semiconductor substrate. A micro-lens module is formed under the color filter. The carrier substrate is removed.

Abstract: A chip package includes a chip, a first adhesive layer, a second adhesive layer, and a protection cap. The chip has a sensing area, a first surface, a second surface that is opposite to the first surface, and a side surface adjacent to the first and second surfaces. The sensing area is located on the first surface. The first adhesive layer covers the first surface of the chip. The second adhesive layer is located on the first adhesive layer, such that the first adhesive layer is between the first surface and the second adhesive layer. The protection cap has a bottom board and a sidewall that surrounds the bottom board. The bottom board covers the second adhesive layer, and the sidewall covers the side surface of the chip.

Abstract: A chip package including a substrate that has a first surface and a second surface opposite thereto is provided. The substrate includes a chip region and a scribe line region that extends along the edge of the chip region. The chip package further includes a dielectric layer disposed on the first surface of the substrate. The dielectric layer corresponding to the scribe line region has a through groove that extends along the extending direction of the scribe line region. A method of forming the chip package is also provided.

Abstract: Embodiments provide a chip device package and a method for fabricating thereof. A semiconductor chip has a substrate. A supporting brick is separated from the substrate by a certain distance. A bonding pad having a surface is disposed across the substrate and the supporting brick. A bonding wire is electrically connected to the bonding pad.

Abstract: A manufacturing method of a passive component structure includes the following steps. A protection layer is formed on a substrate, and bond pads of the substrate are respectively exposed through protection layer openings. A conductive layer is formed on the bond pads and the protection layer. A patterned photoresist layer is formed on the conductive layer, and the conductive layer adjacent to the protection layer openings is exposed through photoresist layer openings. Copper bumps are respectively electroplated on the conductive layer. The photoresist layer and the conductive layer not covered by the copper bumps are removed. A passivation layer is formed on the copper bumps and the protection layer, and at least one of the copper bumps is exposed through a passivation layer opening. A diffusion barrier layer and an oxidation barrier layer are chemically plated in sequence on the copper bump.

Abstract: A chip package including a substrate is provided. A sensing region or device region of the substrate is electrically connected to a conducting pad. A first insulating layer is disposed on the substrate. A redistribution layer is disposed on the first insulating layer. A first portion and a second portion of the redistribution layer are electrically connected to the conducting pad. A second insulating layer conformally extends on the first insulating layer, and covers side surfaces of the first portion and the second portion. A protection layer is disposed on the second insulating layer. A portion of the second insulating layer is located between the protection layer and the first insulating layer. A method of forming the chip package is also provided.

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first isolation layer is formed on a first surface of a wafer substrate. A conductive pad is formed on the first isolation layer. A hollow region through the first surface and a second surface of the wafer substrate is formed, such that the first isolation layer is exposed through the hollow region. A laser etching treatment is performed on the first isolation layer that is exposed through the hollow region, such that a first opening is formed in the first isolation layer, and a concave portion exposed through the first opening is formed in the conductive pad.

Abstract: A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing or device region which is adjacent to the first surface. A recess is in the substrate. The recess extends from the second surface towards the first surface, and vertically overlaps the sensing or device region. A redistribution layer is electrically connected to the sensing or device region, and extends from the second surface into the recess. A method of forming the chip package is also provided.

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first isolation layer is formed on a first surface of a wafer substrate. A conductive pad is formed on the first isolation layer. A hollow region through the first surface and a second surface of the wafer substrate is formed, such that the first isolation layer is exposed through the hollow region. A laser etching treatment is performed on the first isolation layer that is exposed through the hollow region, such that a first opening is formed in the first isolation layer, and a concave portion exposed through the first opening is formed in the conductive pad.

Abstract: An embodiment of this invention provides a separation apparatus for separating a stacked article, such as a semiconductor chip package with sensing functions, comprising a substrate and a cap layer formed on the substrate. The separation apparatus comprises a vacuum nozzle head including a suction pad having a top surface and a bottom surface, a through hole penetrating the top surface and the bottom surface of the suction pad, and a hollow vacuum pipe connecting the through hole to a vacuum pump; a stage positing under the vacuum nozzle head and substantially aligning with the suction pad; a control means coupling to the vacuum nozzle head to lift upward or lower down the vacuum nozzle head; and a first cutter comprising a first cutting body and a first knife connecting to the first cutting body.

Abstract: A chip package includes a substrate, an isolation layer, a redistribution layer, a passivation layer, a first conductive layer, a second conductive layer, and a conductive structure. The isolation layer is located on the substrate. The redistribution layer is located on the isolation layer. The passivation layer is located on the isolation layer and the redistribution layer. The passivation layer has an opening, a wall surface that surrounds the opening, and a surface that faces away from the isolation layer. A portion of the redistribution layer is exposed through the opening. The first conductive layer is located on the redistribution layer that is in the opening, and extends to the wall surface and the surface of the passivation layer. The second conductive layer covers the first conductive layer. The conductive structure is located on the second conductive layer and protrudes from the passivation layer.

Abstract: A chip package includes a chip, a first adhesive layer, a second adhesive layer, and a protection cap. The chip has a sensing area, a first surface, a second surface that is opposite to the first surface, and a side surface adjacent to the first and second surfaces. The sensing area is located on the first surface. The first adhesive layer covers the first surface of the chip. The second adhesive layer is located on the first adhesive layer, such that the first adhesive layer is between the first surface and the second adhesive layer. The protection cap has a bottom board and a sidewall that surrounds the bottom board. The bottom board covers the second adhesive layer, and the sidewall covers the side surface of the chip.

Abstract: A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 ?m to 750 ?m, and the wall surface of the dam element surrounding the sensing area is a rough surface.

Abstract: An optical cover plate for image sensor package includes a transparent substrate, at least an annular dam structure, and a barrier layer. The annular dam structure is disposed on the transparent substrate and encompasses a light-receiving area. The barrier layer conformally covers at least a sidewall of the annular dam structure. A method of manufacturing the optical cover plate, an image sensor package and fabrication method thereof are also disclosed.

Abstract: A chip package includes a chip, a dam element, and a height-increasing element. The chip has an image sensing area, a first surface, and a second surface opposite to the first surface. The image sensing area is located on the first surface of the chip. The dam element is located on the first surface of the chip and surrounds the image sensing area. The height-increasing element is located on the dam element, such that the dam element is between the height-increasing element and the chip.

Abstract: A method for forming a chip package is provided. The method includes providing a substrate and a capping layer, wherein the substrate has a sensing device therein adjacent to a surface of the substrate. The capping layer is attached to the surface of the substrate by an adhesive layer, wherein the adhesive layer covers the sensing device. A dicing process is performed on the substrate, the adhesive layer, and the capping layer along a direction to form individual chip packages.

Abstract: A chip package including a semiconductor substrate is provided. A recess is in the semiconductor substrate and adjoins a side edge of the semiconductor substrate, wherein the semiconductor substrate has at least one spacer protruding from the bottom of the recess. A conducting layer is disposed on the semiconductor substrate and extends into the recess.

Abstract: A lock is provided, including a shell body, a lock main body and an abutting assembly. The shell body is for being fixedly disposed on an object. The lock main body has a first end and a second end which is opposite to the first end, the second end has a first engaging portion, the lock main body is releasably and rotatably inserted into the shell body along a first direction, and the first direction is defined as a connection between the first end and the second end. The abutting assembly has a base, a second engaging portion, which is connected to the base and positionably engaged with the first engaging portion, and a lock plate which is connected to the base and driven by the lock main body, and the lock plate is for being optionally locked with the object.