Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

Abstract: A lock is provided, including: a housing; a latch member, movably mounted to the housing and including a first blocking portion; a blocking member, movably mounted to the housing and including a second blocking portion; a locking member, operably mounted to the housing; wherein when the locking member is in a locking state and the latch member is in a first position, the locking member and the blocking member are free of blocking from each other so that the first blocking portion and the second blocking portion are blocked with each other, and the latch member is unmovable toward a second position; when the locking member is in a unlocked state, the second blocking portion and the first blocking portion are unblocked with each other and the latch member is movable to the second position so that the latch member is retractable from a locked object.

Abstract: A connection lock is provided. A driving assembly is disposed to a shell body, is movable to be in first or second positions and further has a restricting portion. A lock device is disposed to the shell body and includes a lock member which is movable relative to the shell body to be in unlocked or locked positions and has a tendency to move toward the locked position. An actuating member is slidably disposed in the shell body. A first elastic member is disposed in the shell body and abuts against one of the actuating member and the driving assembly to bias the driving assembly in a direction toward the first position. A engaging assembly is disposed in the shell body and is movable to be in released or engaged positions and is configured to be inserted into an anti-theft hole of an object.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

Abstract: A lock is provided, including a sleeve member, a main body and an engaging member. The main body is rotatably disposed in the sleeve member and has a first connecting portion, one of the main body and the sleeve member has a slide slot which extends along an axial direction and the other has a protrusive block, when the protrusive block corresponds to the slide slot in the axial direction, the main body is movable relative to detachable from the sleeve member. The engaging member is rotatably disposed in the sleeve member and has a second connecting portion, one of the engaging member and the main body has a hook and the other has a slot, when the first and second connecting portions are assembled to each other, the engaging member and the main body are co-rotatable, and the hook is engaged with the slot.

Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.

Abstract: A chip package including a substrate, a first conductive structure, and an electrical isolation structure is provided. The substrate has a first surface and a second surface opposite the first surface), and includes a first opening and a second opening surrounding the first opening. The substrate includes a sensor device adjacent to the first surface. A first conductive structure includes a first conductive portion in the first opening of the substrate, and a second conductive portion over the second surface of the substrate. An electrical isolation structure includes a first isolation portion in the second opening of the substrate, and a second isolation portion extending from the first isolation portion and between the second surface of the substrate and the second conductive portion. The first isolation portion surrounds the first conductive portion.

Abstract: A method for manufacturing a semiconductor structure includes the following steps. A first carrier is adhered to a first surface of a wafer by a first temporary bonding layer. A second surface of the wafer facing away from the first carrier is etched to form at least one through hole and at least one trench, in which a conductive pad of the wafer is exposed through the through hole. An isolation layer is formed on the second surface of the wafer, a sidewall of the through hole, and a sidewall of the trench. A second carrier is adhered to the second surface of the wafer by a second temporary bonding layer, and thus the through hole and the trench are covered by the second carrier. The first carrier and the first temporary bonding layer are removed.

Abstract: A connection lock includes an adapting assembly including an outer sleeve and an adapting member, a first connecting member including a first outer tube and a first cable, a lock structure connected to the first cable, second connecting members each including a second outer tube and a second cable, and engaging structures for anti-thefting of a 3C product. The first outer tube is connected with the outer sleeve, and the first cable is connected to the adapting member. The lock structure is movable to a locked position or an unlocked position. Each second outer tube is connected with the outer sleeve, and each second cable is connected to the adapting member. Each engaging structure is connected to one said second cable and movable between an engaged position and a released position so that each engaging structure, the adapting member and the lock structure are comovable.

Abstract: A chip package including a substrate that has a first surface and a second surface opposite thereto is provided. The substrate includes a chip region and a scribe line region that extends along the edge of the chip region. The chip package further includes a dielectric layer disposed on the first surface of the substrate. The dielectric layer corresponding to the scribe line region has a through groove that extends along the extending direction of the scribe line region. A method of forming the chip package is also provided.

Abstract: An electronic device package and fabrication method thereof is provided. First, a semiconductor substrate is provided and the upper surface of it is etched to from recesses. A first isolation layer is formed on the upper surface and the sidewalls of the recesses. A conductive part is formed to fulfill the recesses and a conductive pad is formed on the first isolation layer to connect the conductive part. An electronic device is combined with the semiconductor substrate on the supper surface, wherein the electronic device has a connecting pad electrically connected to the conductive pad. The semiconductor substrate is thinned form its lower surface to expose the conductive part. A second isolation layer is formed below the lower surface and has an opening to expose the conductive part. A redistribution metal line is formed below the second isolation layer and in the opening to electrically connect to the conductive part.

Abstract: The present disclosure provides a carrying structure for carrying electronic device. The carrying structure comprises a carrying base, a start-up member, a linkage module, a latch member, a first buckle member, and a releasing member. When an electronic device is disposed to the carrying base, the electronic device drives the start-up member, which drives the latch member via the linkage module so that the latch member can fix the electronic device to the carrying base. To disassemble the electronic device from the carrying base, press the releasing member, which pushes the first buckle member and makes the latch member depart from the first buckle member and restore to the original position. Consequently, the start-up member and the linkage module can restore to the original positions. Thereby, the effects of rapid assembling and disassembling can be achieved.

Abstract: A connection lock includes an adapting assembly including an outer sleeve and an adapting member, a first connecting member including a first outer tube and a first cable, a lock structure connected to the first cable, second connecting members each including a second outer tube and a second cable, and engaging structures for anti-thefting of a 3C product. The first outer tube is connected with the outer sleeve, and the first cable is connected to the adapting member. The lock structure is movable to a locked position or an unlocked position. Each second outer tube is connected with the outer sleeve, and each second cable is connected to the adapting member. Each engaging structure is connected to one said second cable and movable between an engaged position and a released position so that each engaging structure, the adapting member and the lock structure are comovable.

Abstract: A method for manufacturing a semiconductor structure includes the following steps. A first carrier is adhered to a first surface of a wafer by a first temporary bonding layer. A second surface of the wafer facing away from the first carrier is etched to form at least one through hole and at least one trench, in which a conductive pad of the wafer is exposed through the through hole. An isolation layer is formed on the second surface of the wafer, a sidewall of the through hole, and a sidewall of the trench. A second carrier is adhered to the second surface of the wafer by a second temporary bonding layer, and thus the through hole and the trench are covered by the second carrier. The first carrier and the first temporary bonding layer are removed.

Abstract: A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing or device region which is adjacent to the first surface. A recess is in the substrate. The recess extends from the second surface towards the first surface, and vertically overlaps the sensing or device region. A redistribution layer is electrically connected to the sensing or device region, and extends from the second surface into the recess. A method of forming the chip package is also provided.