Abstract: A chip package including a substrate, a first conductive structure, and an electrical isolation structure is provided. The substrate has a first surface and a second surface opposite the first surface), and includes a first opening and a second opening surrounding the first opening. The substrate includes a sensor device adjacent to the first surface. A first conductive structure includes a first conductive portion in the first opening of the substrate, and a second conductive portion over the second surface of the substrate. An electrical isolation structure includes a first isolation portion in the second opening of the substrate, and a second isolation portion extending from the first isolation portion and between the second surface of the substrate and the second conductive portion. The first isolation portion surrounds the first conductive portion.

Abstract: A lock is provided, including a sleeve member, a main body and an engaging member. The main body is rotatably disposed in the sleeve member and has a first connecting portion, one of the main body and the sleeve member has a slide slot which extends along an axial direction and the other has a protrusive block, when the protrusive block corresponds to the slide slot in the axial direction, the main body is movable relative to detachable from the sleeve member. The engaging member is rotatably disposed in the sleeve member and has a second connecting portion, one of the engaging member and the main body has a hook and the other has a slot, when the first and second connecting portions are assembled to each other, the engaging member and the main body are co-rotatable, and the hook is engaged with the slot.

Abstract: A connection lock is provided. A driving assembly is disposed to a shell body, is movable to be in first or second positions and further has a restricting portion. A lock device is disposed to the shell body and includes a lock member which is movable relative to the shell body to be in unlocked or locked positions and has a tendency to move toward the locked position. An actuating member is slidably disposed in the shell body. A first elastic member is disposed in the shell body and abuts against one of the actuating member and the driving assembly to bias the driving assembly in a direction toward the first position. A engaging assembly is disposed in the shell body and is movable to be in released or engaged positions and is configured to be inserted into an anti-theft hole of an object.

Abstract: The present application discloses a semiconductor product grading method and grading system. The grading method includes: at the time of an electric property test, classifying the several semiconductor products into a plurality of groups according to several test parameters obtained from the test; carrying out a principal component analysis on the corresponding several test parameters in each group, to obtain eigen parameters for each group; and determining, based on the eigen parameters, grades for the semiconductor products in each group. The semiconductor products in each group are graded through several eigen parameters with similar attributes, so the accuracy of the existing semiconductor product grading is improved and the semiconductor products that meet different customer requirements can be accurately and quickly screened out for shipping.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.

Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.

Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.

Abstract: A connection lock is provided, including: a driving member, movable between first and second positions; a locking device by which the driving member is restrictable in the second position; a first housing; an actuating assembly, movably mounted to the first housing and assembled with the driving member; a blocking assembly, mounted to the first housing and movable between release and blocking positions; an electronic transmission unit, connected to the first housing; when the driving member is in the first position, the actuating assembly is driven by the driving member to drive the blocking assembly to the release position, the blocking assembly is detachable from an anti-theft hole; when the driving member is in the second position, the driving member drives the actuating assembly and the actuating assembly restricts the blocking assembly in the blocking position so that the blocking assembly is undetachable from the anti-theft hole.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

Abstract: A lock is provided, including: a housing; a latch member, movably mounted to the housing and including a first blocking portion; a blocking member, movably mounted to the housing and including a second blocking portion; a locking member, operably mounted to the housing; wherein when the locking member is in a locking state and the latch member is in a first position, the locking member and the blocking member are free of blocking from each other so that the first blocking portion and the second blocking portion are blocked with each other, and the latch member is unmovable toward a second position; when the locking member is in a unlocked state, the second blocking portion and the first blocking portion are unblocked with each other and the latch member is movable to the second position so that the latch member is retractable from a locked object.

Abstract: A connection lock is provided. A driving assembly is disposed to a shell body, is movable to be in first or second positions and further has a restricting portion. A lock device is disposed to the shell body and includes a lock member which is movable relative to the shell body to be in unlocked or locked positions and has a tendency to move toward the locked position. An actuating member is slidably disposed in the shell body. A first elastic member is disposed in the shell body and abuts against one of the actuating member and the driving assembly to bias the driving assembly in a direction toward the first position. A engaging assembly is disposed in the shell body and is movable to be in released or engaged positions and is configured to be inserted into an anti-theft hole of an object.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

Abstract: A lock is provided, including a sleeve member, a main body and an engaging member. The main body is rotatably disposed in the sleeve member and has a first connecting portion, one of the main body and the sleeve member has a slide slot which extends along an axial direction and the other has a protrusive block, when the protrusive block corresponds to the slide slot in the axial direction, the main body is movable relative to detachable from the sleeve member. The engaging member is rotatably disposed in the sleeve member and has a second connecting portion, one of the engaging member and the main body has a hook and the other has a slot, when the first and second connecting portions are assembled to each other, the engaging member and the main body are co-rotatable, and the hook is engaged with the slot.

Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.