Chia-Wei Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: A semiconductor device includes a substrate, a fin structure protruding from the substrate, a gate insulating layer covering a channel region formed of the fin structure, a gate electrode layer covering the gate insulating layer, and isolation layers disposed on opposite sides of the fin structure. The fin structure includes a bottom portion, a neck portion, and a top portion sequentially disposed on the substrate. A width of the neck portion is less than a width of the bottom portion and a width of a portion of the top portion.
Abstract: Disclosed herein is a mobile plastic recycling system mounted in a vehicle. The system is configured to process a plastic article and make it into thermoplastic items. The mobile plastic recycling system includes a plastic recycling apparatus and a power supply apparatus that are electrically coupled with each other; the system also includes a vehicle configured to carry and transport the power supply apparatus and plastic recycling apparatus.
Abstract: The driving system for driving a display panel includes a timing controller and a source driving circuit. The source driving circuit includes a plurality of output channels and a plurality of shift registers respectively corresponding to the output channels. The plurality of shift registers are classified into a plurality of shift register series, among which a first shift register series includes a first shift register being as one end and a second shift register being as the other end, and a second shift register series includes a third shift register being as one end and a fourth shift register being as the other end. The timing controller is connected to the first shift register, the second shift register, the third shift register, and the fourth shift register, and transmits a first start pulse to the first shift register and a second start pulse to the third shift register.
Abstract: A light-emitting device includes a first semiconductor layer having an uppermost surface and a bottommost surface; a first light-emitting structure and a second light-emitting structure formed on the same first semiconductor layer, wherein the first semiconductor layer is continuous; a first trench formed between the first and the second light-emitting structures; and a second electrode formed on the second semiconductor layer and including a second pad and a plurality of second extending parts extending from the second pad; wherein the second pad is between the first and the second light-emitting structures, and the plurality of second extending parts extends to the first and the second light-emitting structures, respectively; wherein the first trench passes through the uppermost surface but does not extend to the bottommost surface; wherein the first trench includes an equal width in a top view.
Abstract: Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.
Abstract: A fingerprint recognition device includes a light-transmissible substrate, a plurality of sensing elements, a set of conductive lines and a fingerprint recognition chip. The sensing elements are disposed and the set of conductive lines are an upper surface of the light-transmissible substrate. The fingerprint recognition chip is also disposed on the upper surface of the light-transmissible substrate, and is connected to the sensing elements through the set of conductive lines. The fingerprint recognition chip drives the sensing elements, receives a plurality of sensing results generated by the sensing elements, and accordingly determines a user fingerprint.
Abstract: An automatic uploading method, comprising the steps of: receiving a wake-up signal by a low-power-consumption wireless transmission module of a portable information capturing device; actuating a high-power-consumption wireless transmission module of the portable information capturing device according to the wake-up signal; creating a connection between the high-power-consumption wireless transmission module and a first relay station after the high-power-consumption wireless transmission module has been actuated; shutting down the low-power-consumption wireless transmission module after the connection has been created; and transmitting, via the connection, an upload data of the portable information capturing device to a second relay station, wherein the second relay station is connected to the first relay station.
Abstract: A heat dissipation assembly includes a pressing unit and a heat dissipation module. The pressing unit includes a pressing plate, a plurality of elastic cantilevers and contacting members. The pressing plate can be secured on a bottom plate so that a heat source can be sandwiched between the pressing plate and the bottom plate. The elastic cantilevers are respectively disposed on the pressing plate and protruded outwards from the pressing plate to be suspended in midair. The contacting members are respectively disposed on the elastic cantilevers for abutting the bottom plate. The heat dissipation module is fixedly connected to the pressing plate and a carrier member for thermally guiding the heat source.
April 13, 2017
Date of Patent:
June 18, 2019
Quanta Computer Inc.
Chih-Chao Chen, Pei-Yu Chang, Chia-Hung Ma, Chih-Wei Jen
Abstract: Embodiments disclose a device for testing biological specimen. The device includes a sample carrier and a detachable cover. The sample carrier includes a specimen holding area. The detachable cover is placed on top of the specimen holding area. The detachable cover includes a magnifying component configured to align with the specimen holding area. The focal length of the magnifying component is from 0.1 mm to 8.5 mm. The magnifying component has a linear magnification ratio of at least 1. Some embodiments further include a multi-camera configuration. These embodiments include a first camera module and a second camera module arranged to capture one or more images of the first holding area and the second holding area, respectively. The processor may perform different analytic processes on the captured images of different holding areas to determine an outcome with regard to the biological specimen.
Abstract: A light-emitting device includes a first semiconductor layer; a first, a second and a third light-emitting structures formed on the same first semiconductor layer; a first trench between the first and the second light-emitting structures; a second trench between the second and the third light-emitting structures, wherein the first and the second trenches include bottom portions exposing a surface of the first semiconductor layer; a third trench in one of the light-emitting structures, exposing the first semiconductor layer and extending along a direction parallel with the first semiconductor layer; an insulating bridge part in the first and the second trenches, connecting the light-emitting structures; a first electrode in the third trench, electrically connecting to the first semiconductor layer; and a second electrode, including a pad on one of the light-emitting structures and an extending part; wherein the extending part is formed on the insulating bridge part and extends to the light-emitting structures.
Abstract: A semiconductor memory device is provided, and which includes a substrate, plural gates, plural plugs, a capacitor structure and a conducting cap layer. The gates are disposed within the substrate, and the plugs are disposed on the substrate, with each plug electrically connected to two sides of each gate on the substrate. The capacitor structure is disposed on the substrate, and the capacitor structure includes plural capacitors, with each capacitor electrically connected to the plugs respectively. The conducting cap layer covers the top surface and sidewalls of the capacitor structure. Also, the semiconductor memory device further includes an adhesion layer and an insulating layer. The adhesion layer covers the conducting cap layer and the capacitor structure, and the insulating layer covers the adhesion layer.
May 22, 2018
Date of Patent:
June 4, 2019
UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
Abstract: A patterned sapphire substrate has a first surface and a second surface opposite to each other, in which, the first surface of the substrate is formed by arranging a plurality of interspaced patterns, wherein, the patterns have a top surface, a bottom surface and a plurality of side surfaces and at least one concave region sandwiched between the adjacent side surfaces and the top surface, where, depth and width of the concave region gradually decrease from the top to the bottom of the pattern. The concave region on the pattern surface of the patterned sapphire substrate enlarges light reflection area, thus improving light extraction efficiency of the patterned sapphire substrate.
October 3, 2017
Date of Patent:
June 4, 2019
XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
Abstract: An SRAM structure is provided. The SRAM structure includes a plurality of first well regions with a first doping type, a plurality of second well regions with a second doping type, a third well region with the second doping type, a plurality of first well pick-up regions, a plurality of second well pick-up regions, and a plurality of memory cells. The first well regions, the second well regions, and the third well region are formed in a semiconductor substrate. The third well region is adjacent to the second well regions. The first well pick-up regions are formed in the first well regions. The second well pick-up regions are formed in the third well region. The second well pick-up regions are shared by the third well region and the second well regions. The memory cells are formed on the first and second well regions.
April 16, 2018
May 30, 2019
Feng-Ming CHANG, Chia-Hao PAO, Lien-Jung HUNG, Ping-Wei WANG
Abstract: A composite cable assembly includes flat cables, a cable unit and fastening units. Each flat cable includes conductor assemblies and a shielding layer covering the conductor assemblies. The cable unit includes transmission lines. The transmission lines are arranged horizontally and in contact with the shielding layer of the flat cable closest to the transmission lines. The cable unit contacts the flat cable closest to the cable unit, the cable unit and each flat cable are together bent to form bent portions and extension sections connected to the bent portions. Each two fastening units are arranged spaced apart at two sides of a corresponding bent portion. Each extension section has the same length when the cable unit and each flat cable are moved in a movement direction to extend or collapse.
Abstract: A key apparatus includes a substrate, a keycap, a balancing lever, and a membrane layer. The keycap is disposed on the substrate. The balancing lever is disposed between the substrate and the keycap. The balancing lever includes a shaft lever and a side lever extending from a side direction of the shaft lever. The side lever has an end away from the shaft lever. The membrane layer is disposed on the substrate. The membrane layer is provided with a cutting structure. The cutting structure is close to the end of the side lever. The membrane layer further includes a flexible limiting area located on one side of the cutting structure. The side lever of the balancing lever is inserted in the cutting structure, and makes the end be held against the flexible limiting area.
Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.
Abstract: Semiconductor devices and a method for forming the same are provided. In various embodiments, a method for forming a semiconductor device includes receiving a semiconductor substrate including a channel. An atmosphere-modulation layer is formed over the channel. An annealing process is performed to form an interfacial layer between the channel and the atmosphere-modulation layer.
Abstract: An integrated circuit for driving a display panel is provided. The integrated circuit includes a gamma mapping circuit and a mura compensation circuit. The gamma mapping circuit is configured to receive a gray level of an image data, map the gray level to a gamma code according to at least one gamma table, and output the gamma code. The mura compensation circuit is configured to receive the gamma code, and compensate the gamma code according to at least one de-mura table to generate a compensation result after the gamma mapping circuit performs the step of mapping the gray level to the gamma code. The integrated circuit drives the display panel according to the compensation result. In addition, a method for driving a display panel is also provided.
February 8, 2018
Date of Patent:
May 7, 2019
Novatek Microelectronics Corp.
I-Te Liu, Chia-Wei Chang, Chien-Yu Chen, Hsien-Wen Lo