Patents by Inventor Chia-Wei Chang

Chia-Wei Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250095539
    Abstract: An adaptive multi-area frame rate display system and a method employed are provided. The method includes: dividing a display panel into a plurality of display areas and setting a plurality of compensation parameter sets corresponding to a plurality of frame rates; receiving display stream data; controlling the plurality of display areas of the display panel to display an image corresponding to the display stream data; performing a multi-area frame rate calculation operation to obtain a frame rate of each of the plurality of display areas; and, for each of the display areas, applying the compensation parameter set to which the frame rate of each of the display areas corresponds, so as to compensate an image subsequently displayed in each of the display areas.
    Type: Application
    Filed: May 15, 2024
    Publication date: March 20, 2025
    Applicant: Novatek Microelectronics Corp.
    Inventors: Yen-Ju Hou, Chang-Sheng Tseng, Chia-Wei Chang
  • Publication number: 20250091540
    Abstract: A vehicle prevention airbag system includes an airbag prevention device and a threat detection device including a collision assessment unit and a sensor module for detecting threat objects or obstacles approaching the vehicle and to assess the collision probability between the threat object or obstacle and the vehicle. The airbag prevention device includes an airbag expansion controller and an external airbag module. When collision probability between the threat object and the vehicle is equal to or greater than a safety threshold, the threat detection device establishes a first collision determination message. The airbag prevention device expands at least one prevention airbag in the direction corresponding to the impact based on the first collision determination message. When the vehicle is impacted and may collide with an obstacle, a second collision determination message is established. The external airbag is expanded in the direction corresponding to the second collision determination message.
    Type: Application
    Filed: September 18, 2024
    Publication date: March 20, 2025
    Inventor: Chia-Wei Chang
  • Publication number: 20250053343
    Abstract: An apparatus can include a number of memory devices and a memory controller coupled to one or more of the number of memory devices. The memory controller can include a row hammer detector. The memory controller can be configured increment for a first time period a row counter in a first data structure and a refresh counter. The memory controller can be configured to increment for a second time period a row counter in a second data structure and the refresh counter. The memory controller can be configured to determine that a value of the refresh counter exceeds a refresh threshold and responsive to the determination that the value of the refresh counter exceeds the refresh threshold, issue a notification.
    Type: Application
    Filed: October 28, 2024
    Publication date: February 13, 2025
    Inventors: Amitava Majumdar, Anandhavel Nagendrakumar, Mohammed Ebrahim Hargan, Scott Garner, Danilo Caraccio, Daniele Balluchi, Chia Wei Chang, Ankush Lal
  • Publication number: 20250055437
    Abstract: An electronic device includes a shared pin and a bandwidth extension circuit. The electronic device receives or transmits a signal through the shared pin. The bandwidth extension circuit is electrically coupled to the shared pin. The bandwidth extension circuit includes a first inductor, a second inductor, a first capacitor, a second capacitor, and a third capacitor. The first inductor is electrically connected between the shared pin and a node. The second inductor is electrically connected to the first inductor through the node. The first capacitor is electrically connected between the node and a ground. The second capacitor is electrically connected between the shared pin and the ground. The third capacitor is electrically connected between the second inductor and the ground. The first inductor is different from the second inductor. There is no coupling effect between the first inductor and the second inductor.
    Type: Application
    Filed: January 2, 2024
    Publication date: February 13, 2025
    Inventors: Did-Min SHIH, Chia-Wei CHANG, Yen-Wei WU
  • Patent number: 12203098
    Abstract: Provided are methods and compositions for obtaining functionally enhanced derivative effector cells obtained from directed differentiation of genomically engineered iPSCs. Also provided are derivative cells having stable and functional genome editing that delivers improved or enhanced therapeutic effects. Further provided are therapeutic compositions and the use thereof comprising the functionally enhanced derivative effector cells alone, or with antibodies or checkpoint inhibitors in combination therapies.
    Type: Grant
    Filed: June 30, 2023
    Date of Patent: January 21, 2025
    Assignee: FATE THERAPEUTICS, INC.
    Inventors: Bahram Valamehr, Tom Tong Lee, Martin Hosking, Eigen Peralta, Chia-Wei Chang
  • Publication number: 20250024383
    Abstract: This disclosure provides systems, methods, and devices for wireless communication that support transmission of power limit indications for a UE associated with different frequency bands. In a first aspect, a method of wireless communication includes detecting a first trigger condition for transmission of at least a first indication of a first transmission power limit of the UE and a second indication of a second transmission power limit of the UE, wherein the first transmission power limit is associated with a first frequency band supported by the UE and the second transmission power limit is associated with a second frequency band supported by the UE and transmitting, to a first network node associated with the first frequency band, the first indication and the second indication in accordance with detection of the first trigger condition. Other aspects and features are also claimed and described.
    Type: Application
    Filed: July 11, 2023
    Publication date: January 16, 2025
    Inventors: Chan-Jui Chian, Chia-Wei Chang, Tzui Lu, Tsung-Te Hou, Kai-Chun Huang, Wei-Che Chang, Yuwei Pan, Cheng-Ting Tsai
  • Publication number: 20250016964
    Abstract: A node unit includes a base plate, at least one function module, and a non-conductive coolant. The function module includes a heat-generating element, a heat-dissipating structure, and a pump. The heat-generating element is disposed on the base plate, the heat-dissipating structure is disposed on the heat-generating element, and the pump is disposed on the heat-dissipating structure. The base plate and the at least one function module are immersed in the non-conductive coolant. The pump is configured to drive the non-conductive coolant to flow into the heat-dissipating structure and discharge from the heat-dissipating structure. An electronic device and an immersion cooling type equipment are also mentioned.
    Type: Application
    Filed: September 1, 2023
    Publication date: January 9, 2025
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Yu-Wen Chung, Shun-Wei Yang, Heng-Yu Lee, Hao-Yuan Cheng, Chun-Shi Liu, Chia-Wei Chang
  • Publication number: 20250006659
    Abstract: Methods for reducing warpage and increasing the effectiveness of hybrid bond void testing are disclosed. A semiconductor package has a first side and a second side, with a dummy bond pad located on the second side, and at least one metal-containing layer between the first side and the second side (for example a redistribution layer). A warpage control structure is provided in the semiconductor package that extends from the first side into the semiconductor package, and is aligned with the dummy bond pad. The warpage control structure is made of a low-density filling. This relieves stress that causes/increases warpage. When a hybrid bond is formed between the semiconductor package and another semiconductor package, the warpage control structure maximizes acoustic wave penetration for testing the quality of the hybrid bond at the dummy bond pad.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Inventors: Ji-Feng Ying, Xuewen Tang, Wen-Hsien Chuang, Jyun-Lin Wu, Chia Wei Chang
  • Publication number: 20240427518
    Abstract: An example apparatus can include a program component. The program component can program each of a plurality of planes during different time periods subsequent to performing a multi-plane programming on a non-volatile memory array. The program component can monitor a program pulse count for each of the respective plurality of planes per super block. The program component can, in response to the program pulse count for a respective block within one of the plurality of planes being above a threshold pulse count, determine that the respective block is a bad block.
    Type: Application
    Filed: May 31, 2024
    Publication date: December 26, 2024
    Inventors: Chia Wei Chang, Chia Yu Kuo, Tzu Ting Tseng, Pinhsueh Lai
  • Patent number: 12176385
    Abstract: A semiconductor device may include a compound substrate and a 3-dimensional inductor structure. The compound substrate may include a front surface and a back surface. The 3-dimensional inductor structure may include a front conductive stack, a back conductive layer, and at least one through-hole structure. At least one portion of the front conductive stack may include a first conductive layer disposed on the front surface of the compound substrate, and a second conductive layer disposed on the first conductive layer. The second conductive layer has a thickness ranging between 30 micrometers and 400 micrometers. The back conductive layer is disposed on the back surface of the compound substrate. The at least one through-hole structure penetrates through the compound substrate, and electrically connects the front conductive stack to the back conductive layer.
    Type: Grant
    Filed: November 20, 2022
    Date of Patent: December 24, 2024
    Assignee: RichWave Technology Corp.
    Inventors: Chia-Wei Chang, Yan-Han Huang, Chin-Chia Chang
  • Publication number: 20240404973
    Abstract: An example semiconductor device package includes a semiconductor die having bond pads on a device side surface, and a build-up routing layer on the semiconductor die including: connection level conductors directly contacting the bond pads; trace level conductors on the connection level conductors directly contacting distal ends of the connection level conductors; dielectric material surrounding the connection level conductors and the trace level conductors; terminals formed of portions of a top layer of the trace level conductors having a board side surface exposed from the dielectric material, wherein an electrical connection between the terminals and the bond pads is formed without a solder joint or a bond wire; and mold compound covering a portion of the semiconductor die, the trace level conductors and the connection level conductors of the build-up routing layer, wherein the board side surface of the terminals is exposed from the mold compound.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 5, 2024
    Inventors: Mohamad Ashraf bin Mohd Arshad, Jeffrey Salvacion Solas, Ruby Ann Merto Camenforte, Huay Yann Tay, Chia Wei Chang, Xiaolei Liao
  • Publication number: 20240363730
    Abstract: A semiconductor device includes a substrate, a fin structure protruding from the substrate, a gate insulating layer covering a channel region formed of the fin structure, a gate electrode layer covering the gate insulating layer, and isolation layers disposed on opposite sides of the fin structure. The fin structure includes a bottom portion, a neck portion, and a top portion sequentially disposed on the substrate. A width of the neck portion is less than a width of the bottom portion and a width of a portion of the top portion.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei CHANG, Chiung Wen HSU, Yu-Ting WENG
  • Patent number: 12131071
    Abstract: An apparatus can include a number of memory devices and a memory controller coupled to one or more of the number of memory devices. The memory controller can include a row hammer detector. The memory controller can be configured increment for a first time period a row counter in a first data structure and a refresh counter. The memory controller can be configured to increment for a second time period a row counter in a second data structure and the refresh counter. The memory controller can be configured to determine that a value of the refresh counter exceeds a refresh threshold and responsive to the determination that the value of the refresh counter exceeds the refresh threshold, issue a notification.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: October 29, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Amitava Majumdar, Anandhavel Nagendrakumar, Mohammed Ebrahim Hargan, Scott Garner, Danilo Caraccio, Daniele Balluchi, Chia Wei Chang, Ankush Lal
  • Publication number: 20240355804
    Abstract: A chip-on-wafer-on-substrate (CoWoS) semiconductor assembly is formed which includes a chip-on-wafer (CoW) sub-assembly of integrated circuit (IC) dies mounted on an interposer, which is in turn mounted on a package substrate with a top metallization stack and a bottom metallization stack using bonding bumps connecting the backside of the interposer and the front side of the package substrate. The bonding bumps provide electrical connections between the ends of through-vias exposed at the backside of the interposer and the top metallization stack of the package substrate. The likelihood of certain failure mechanisms that can adversely affect CoWoS yield are reduced or eliminated by ensuring a total metal thickness of the top metallization stack is greater than a total metal thickness of the bottom metallization stack, but not so much greater as to induce cracking of the underfill material during curing thereof.
    Type: Application
    Filed: July 3, 2024
    Publication date: October 24, 2024
    Inventors: Chia-Wei Chang, Ju-Min Chen, Jyun-Lin Wu, Yao-Chun Chuang
  • Patent number: 12068394
    Abstract: A semiconductor device includes a substrate, a fin structure protruding from the substrate, a gate insulating layer covering a channel region formed of the fin structure, a gate electrode layer covering the gate insulating layer, and isolation layers disposed on opposite sides of the fin structure. The fin structure includes a bottom portion, a neck portion, and a top portion sequentially disposed on the substrate. A width of the neck portion is less than a width of the bottom portion and a width of a portion of the top portion.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: August 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Wei Chang, Chiung Wen Hsu, Yu-Ting Weng
  • Patent number: 12068300
    Abstract: A chip-on-wafer-on-substrate (CoWoS) semiconductor assembly is formed which includes a chip-on-wafer (CoW) sub-assembly of integrated circuit (IC) dies mounted on an interposer, which is in turn mounted on a package substrate with a top metallization stack and a bottom metallization stack using bonding bumps connecting the backside of the interposer and the front side of the package substrate. The bonding bumps provide electrical connections between the ends of through-vias exposed at the backside of the interposer and the top metallization stack of the package substrate. The likelihood of certain failure mechanisms that can adversely affect CoWoS yield are reduced or eliminated by ensuring a total metal thickness of the top metallization stack is greater than a total metal thickness of the bottom metallization stack, but not so much greater as to induce cracking of the underfill material during curing thereof.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: August 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Wei Chang, Ju-Min Chen, Jyun-Lin Wu, Yao-Chun Chuang
  • Publication number: 20240191719
    Abstract: A ceiling fan including a fan device and a remote control is provided. The fan device includes a motor and a control unit. The remote control includes a gesture sensing unit and a processing unit. The gesture sensing unit includes a sensing module that is configured to obtain a sense image of an object, and includes a storage medium that stores a plurality of data sets and different reference tracks that respectively correspond to the data sets. The processing unit is configured to: obtain a movement track of the object; obtain a corresponding one of the data sets when the movement track conforms with one of the reference tracks; and output a command that is related to said corresponding one of the data sets to the control unit. In response to receipt of the command, the control unit adjusts rotational speed of the motor according to the command.
    Type: Application
    Filed: April 11, 2023
    Publication date: June 13, 2024
    Applicant: HOTECK INC.
    Inventors: Te-Yi CHEN, Chia-Wei CHANG, Min-Yuan HSIAO
  • Publication number: 20240141916
    Abstract: A ceiling fan and a structure thereof are provided. The structure includes a blade holder, a plurality of blades, and a plurality of positioning elements. The blade holder includes a holder body and a plurality of support platforms. The holder body has a plurality of first matching structures spaced apart from each other. Each of the support platforms includes a first positioning structure. Each of the blades has a second matching structure and a second positioning structure. The second matching structures can be guided by the first matching structures, so that each of the blades is disposed at an installation position on one of the support platforms along an oblique track. When each of the blades is located at the installation position, the first positioning structures and the second positioning structures abut against each other.
    Type: Application
    Filed: May 23, 2023
    Publication date: May 2, 2024
    Inventors: WEN-HAI HUANG, CHIA-WEI CHANG, MIN-YUAN HSIAO
  • Publication number: 20240117380
    Abstract: Provided herein are CRISPR/Cas9 complexes and method of using same.
    Type: Application
    Filed: April 4, 2023
    Publication date: April 11, 2024
    Applicant: THE UAB RESEARCH FOUNDATION
    Inventors: Tim Townes, Lei Ding, Chia-Wei Chang
  • Publication number: 20240113154
    Abstract: A semiconductor device may include a compound substrate and a 3-dimensional inductor structure. The compound substrate may include a front surface and a back surface. The 3-dimensional inductor structure may include a front conductive stack, a back conductive layer, and at least one through-hole structure. At least one portion of the front conductive stack may include a first conductive layer disposed on the front surface of the compound substrate, and a second conductive layer disposed on the first conductive layer. The second conductive layer has a thickness ranging between 30 micrometers and 400 micrometers. The back conductive layer is disposed on the back surface of the compound substrate. The at least one through-hole structure penetrates through the compound substrate, and electrically connects the front conductive stack to the back conductive layer.
    Type: Application
    Filed: November 20, 2022
    Publication date: April 4, 2024
    Applicant: RichWave Technology Corp.
    Inventors: Chia-Wei Chang, Yan-Han Huang, Chin-Chia Chang