Patents by Inventor Chia-Wei Chang

Chia-Wei Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140321672
    Abstract: An electronic device with speakerphone and microphone is provided. The electronic device comprises a housing, a sound input unit, a sound output unit, an audio signal receiving terminal, an acoustic processing unit, a signal line and a sealing member. The housing has a microphone shell, a speaker shell and a soundproof structure. The soundproof structure is connected between the microphone shell and the speaker shell. The soundproof structure has a line output hole. The acoustic processing unit connects the sound input unit and the audio signal receiving terminal respectively to receive and mix two audio signals so as to generate an audio output signal. The audio output signal is transmitted to the sound output unit through a signal line. The sealing member is disposed around the line output hole and seals the line output hole.
    Type: Application
    Filed: April 29, 2014
    Publication date: October 30, 2014
    Applicant: WINTEK CORPORATION
    Inventors: Chia-Hung Yeh, Shyh-Jeng Chen, Yu-Liang Chow, Chia-Wei Chang, Tsung-Yi Lin, Ming-Chuan Lin, Wen-Hung Wang, Shih-Cheng Wang, Hsuan Wang, Chung-Shun Feng, Kuang-Neng Chen, Yin-Zung Wu
  • Publication number: 20140316689
    Abstract: In a method of monitoring an actual distance between a first vehicle and a second vehicle, using a recipient electronic device which is positioned in the second vehicle positioned after the first vehicle, the recipient electronic device calculates the actual distance according to position information of the first and the second vehicles, and reminds a driver of the second vehicle to adjust a driving speed when the actual distance is less than a predetermined value.
    Type: Application
    Filed: October 12, 2013
    Publication date: October 23, 2014
    Applicant: FIH (HONG KONG) LIMITED
    Inventor: CHIA-WEI CHANG
  • Publication number: 20140264491
    Abstract: An integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second dielectric region are on opposite sides of, and in contact with, the semiconductor strip. Each of the first dielectric region and the second dielectric region includes a first portion level with the semiconductor strip, and a second portion lower than the semiconductor strip. The second portion further includes a portion overlapped by the semiconductor strip.
    Type: Application
    Filed: April 19, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Chun Huang, Chih-Tang Peng, Chia-Wei Chang, Ming-Hua Yu, Hao-Ming Lien, Chao-Cheng Chen, Tze-Liang Lee
  • Publication number: 20140252428
    Abstract: An integrated circuit structure includes a semiconductor substrate, an insulation region extending into the semiconductor substrate, and a semiconductor strip between two opposite portions of the insulation region. The semiconductor strip includes an upper portion higher than top surfaces of the insulation regions and a lower portion in the insulation region. The lower portion has a sidewall including a first sidewall portion having a first slope and a second sidewall portion over and connected to the first sidewall portion. The second sidewall portion has a second slope smaller than the first slope.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Wei Chang, Srisuda Thitinun, Ryan Chia-Jen Chen
  • Patent number: 8802510
    Abstract: Methods for forming uniformly spaced and uniformly shaped fine lines in semiconductor processes using double patterning. Dummy lines are formed over a substrate. Sidewall spacer material is deposited over the top and sides of each of the dummy lines. Etching is performed to remove the top surface sidewall spacer material from the tops of the dummy lines. The dummy material is removed by selective etching leaving the spacer material. A photolithographic mask is formed defining inner lines that are desired for a substrate etching step, and temporary lines outside of the desired lines. The temporary lines are partially masked. The temporary lines are partially removed while the inner desired lines are retained. A transfer etch process then patterns an underlying mask layer corresponding to the inner desired lines, and the mask layer is used for etching lines in an underlying semiconductor substrate.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Chang, Ryan Chia-Jen Chen
  • Patent number: 8792078
    Abstract: An apparatus for mounting a pellicle onto a mask is provided. In one embodiment, the apparatus comprises a base provided with a track; a dummy plate holder coupled to the base, the dummy plate holder for receiving a dummy plate having an elevated portion on one side thereof; a mask holder for receiving a mask, the mask holder slidably coupled to the base; a pellicle holder for receiving a pellicle frame, the pellicle holder slidably coupled to the base; and drive means being adapted to drive the pellicle holder along the track towards the dummy plate holder, wherein during operation when the pellicle frame is mounted onto the mask causing the mask to contact the dummy plate, the mounting pressure in the mask is distributed by way of the elevated portion in the dummy plate, thus reducing distortion in the mask.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: July 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ming Lin, Chien-Chao Huang, Jong-Yuh Chang, Chia-Wei Chang, Boming Hsu
  • Publication number: 20140187297
    Abstract: A touch-control accessory having a cleaning function and a cell phone shield carrying the touch-control accessory are disclosed. The cell phone shield includes a shield body having an accommodation chamber surrounded by a back wall and a coupling hole cut through the back wall, and a touch-control accessory detachably mounted in the coupling hole of the shield body and defining an electrically conductive touch-control area for touching the touchscreen of the cell phone to perform touch control functions and a wiping area for cleaning the touchscreen of the cell phone.
    Type: Application
    Filed: January 3, 2013
    Publication date: July 3, 2014
    Applicant: SONMII ENTERPRISE CO., LTD
    Inventors: Chia-Wei Chang, Li-Xuan Sun
  • Publication number: 20140113964
    Abstract: The present invention discloses a method of preventing and treating allergic airway diseases via intranasal gabexate mesilate, comprising administrating a pharmaceutically effective amount of a composition comprising a gabexate mesilate via nasal spray to prevent and treat allergy induced by a serine protease type allergen.
    Type: Application
    Filed: October 23, 2012
    Publication date: April 24, 2014
    Applicant: TAICHUNG VETERANS GENERAL HOSPITAL
    Inventors: MEY-FANN LEE, YI-HSING CHEN, CHIA-WEI CHANG
  • Patent number: 8696366
    Abstract: A connector module includes a female connector and a male connector. The female connector includes a female magnetic part having a jack, an anode contact disposed in the jack, and a cathode contact disposed on the female magnetic part and surrounding the jack. The male connector includes a male magnetic part corresponding to the female magnetic part, an anode plug protruded from the male magnetic part, and a cathode plug disposed on the male magnetic part having a protruding position and an invaginating position in relative to the male magnetic part. When the male magnetic part attracts the female magnetic part, the anode plug is inserted in the jack and is in electrical contact with the anode contact. The cathode plug is in electrical contact with the cathode contact and is moved from the protruding position to the invaginating position. The male connector rotates on the female connector relatively.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: April 15, 2014
    Assignee: Inhon International Co. Ltd.
    Inventors: Chien-Chuan Chen, Kun-Huang Hsu, Chia-Wei Chang
  • Patent number: 8658539
    Abstract: A FinFET device may include a first semiconductor fin laterally adjacent a second semiconductor fin. The first semiconductor fin and the second semiconductor fin may have profiles to minimize defects and deformation. The first semiconductor fin comprises an upper portion and a lower portion. The lower portion of the first semiconductor fin may have a flared profile that is wider at the bottom than the upper portion of the first semiconductor fin. The second semiconductor fin comprises an upper portion and a lower portion. The lower portion of the second semiconductor fin may have a flared profile that is wider than the upper portion of the second semiconductor fin, but less than the lower portion of the first semiconductor fin.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: February 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Chang, Chih-Fang Liu, Chih-Tang Peng, Tai-Chun Huang, Ryan Chia-Jen Chen
  • Publication number: 20130302975
    Abstract: A FinFET device may include a first semiconductor fin laterally adjacent a second semiconductor fin. The first semiconductor fin and the second semiconductor fin may have profiles to minimize defects and deformation. The first semiconductor fin comprises an upper portion and a lower portion. The lower portion of the first semiconductor fin may have a flared profile that is wider at the bottom than the upper portion of the first semiconductor fin. The second semiconductor fin comprises an upper portion and a lower portion. The lower portion of the second semiconductor fin may have a flared profile that is wider than the upper portion of the second semiconductor fin, but less than the lower portion of the first semiconductor fin.
    Type: Application
    Filed: July 15, 2013
    Publication date: November 14, 2013
    Inventors: Chia-Wei Chang, Chih-Fang Liu, Chih-Tang Peng, Tai-Chun Huang, Ryan Chia-Jen Chen
  • Patent number: 8552762
    Abstract: A wire-OR matching circuit with low power consumption can be enabled by inputting an input-enabling signal representing “enabled.” The wire-OR matching circuit generates an output-enabling signal according to a control signal and a periodic pulse signal. When the periodic pulse signal represents “turn on”, if the input-enabling signal represents “enabled” and the control signal represents “not disabled”, the output-enabling signal represents “enabled;” if the input-enabling signal represents “enabled” and the control signal represents “disabled”, the output-enabling signal represents “not enabled.” The wire- or matching circuit can promptly break the connection between the high voltage source and the low voltage source by controlling the pulse width of the periodic pulse signal. In this way, large current is avoided, saving power consumption.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: October 8, 2013
    Assignee: Etron Technology, Inc.
    Inventors: Chia-Wei Chang, Feng-Chia Chang
  • Publication number: 20130260577
    Abstract: A connector module includes a female connector and a male connector. The female connector includes a female magnetic part having a jack, an anode contact disposed in the jack, and a cathode contact disposed on the female magnetic part and surrounding the jack. The male connector includes a male magnetic part corresponding to the female magnetic part, an anode plug protruded from the male magnetic part, and a cathode plug disposed on the male magnetic part having a protruding position and an invaginating position in relative to the male magnetic part. When the male magnetic part attracts the female magnetic part, the anode plug is inserted in the jack and is in electrical contact with the anode contact. The cathode plug is in electrical contact with the cathode contact and is moved from the protruding position to the invaginating position. The male connector rotates on the female connector relatively.
    Type: Application
    Filed: September 12, 2012
    Publication date: October 3, 2013
    Applicant: INHON INTERNATIONAL CO. LTD.
    Inventors: Chien-Chuan Chen, Kun-Huang Hsu, Chia-Wei Chang
  • Patent number: 8546891
    Abstract: A FinFET device may include a first semiconductor fin laterally adjacent a second semiconductor fin. The first semiconductor fin and the second semiconductor fin may have profiles to minimize defects and deformation. The first semiconductor fin comprises an upper portion and a lower portion. The lower portion of the first semiconductor fin may have a flared profile that is wider at the bottom than the upper portion of the first semiconductor fin. The second semiconductor fin comprises an upper portion and a lower portion. The lower portion of the second semiconductor fin may have a flared profile that is wider than the upper portion of the second semiconductor fin, but less than the lower portion of the first semiconductor fin.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: October 1, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Chang, Chih-Fang Liu, Chih-Tang Peng, Tai-Chun Huang, Ryan Chia-Jen Chen
  • Publication number: 20130254886
    Abstract: A method includes determining, at a network routing device, an average packet drop rate for a plurality of aggregations of packet flows. The method also determines a threshold packet drop rate based on the average packet drop rate, a current packet drop rate for a select aggregation of the plurality of aggregations, and whether at least one packet flow of the select aggregation is potentially subject to a denial-of-service attack based on a comparison of the current packet drop rate to the threshold packet drop rate.
    Type: Application
    Filed: May 14, 2013
    Publication date: September 26, 2013
    Applicant: AT&T Intellectual Property I, L.P.
    Inventors: Jia Wang, Chia-Wei Chang, Seungjoon Lee, Bill Lin
  • Publication number: 20130221448
    Abstract: A FinFET device may include a first semiconductor fin laterally adjacent a second semiconductor fin. The first semiconductor fin and the second semiconductor fin may have profiles to minimize defects and deformation. The first semiconductor fin comprises an upper portion and a lower portion. The lower portion of the first semiconductor fin may have a flared profile that is wider at the bottom than the upper portion of the first semiconductor fin. The second semiconductor fin comprises an upper portion and a lower portion. The lower portion of the second semiconductor fin may have a flared profile that is wider than the upper portion of the second semiconductor fin, but less than the lower portion of the first semiconductor fin.
    Type: Application
    Filed: February 29, 2012
    Publication date: August 29, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Chang, Chih-Fang Liu, Chih-Tang Peng, Tai-Chun Huang, Ryan Chia-Jen Chen
  • Publication number: 20130217233
    Abstract: Methods for forming uniformly spaced and uniformly shaped fine lines in semiconductor processes using double patterning. Dummy lines are formed over a substrate. Sidewall spacer material is deposited over the top and sides of each of the dummy lines. Etching is performed to remove the top surface sidewall spacer material from the tops of the dummy lines. The dummy material is removed by selective etching leaving the spacer material. A photolithographic mask is formed defining inner lines that are desired for a substrate etching step, and temporary lines outside of the desired lines. The temporary lines are partially masked. The temporary lines are partially removed while the inner desired lines are retained. A transfer etch process then patterns an underlying mask layer corresponding to the inner desired lines, and the mask layer is used for etching lines in an underlying semiconductor substrate.
    Type: Application
    Filed: February 22, 2012
    Publication date: August 22, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Chang, Ryan Chia-Jen Chen
  • Patent number: 8508000
    Abstract: A FinFET device may include a first semiconductor fin laterally adjacent a second semiconductor fin. The first semiconductor fin and the second semiconductor fin may have profiles to minimize defects and deformation. The first semiconductor fin comprises an upper portion and a lower portion. The lower portion of the first semiconductor fin may have a flared profile that is wider at the bottom than the upper portion of the first semiconductor fin. The second semiconductor fin comprises an upper portion and a lower portion. The lower portion of the second semiconductor fin may have a flared profile that is wider than the upper portion of the second semiconductor fin, but less than the lower portion of the first semiconductor fin.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: August 13, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Chang, Chih-Fang Liu, Chih-Tang Peng, Tai-Chun Huang, Ryan Chia-Jen Chen
  • Publication number: 20130203247
    Abstract: An embodiment of the current disclosure includes a method of providing a substrate, forming a polysilicon layer over the substrate, forming a first photoresist layer on the polysislicon layer, creating a first pattern on the first photoresistlayer, wherein some portions of the polysilicon layer are covered by the first photoresist layer and some portions of the polysilicon layer are not covered by the first photoresist layer, implanting ions into the portions of the polysilicon layer that are not covered by the first photoresist layer, removing the first photoresist layer from the polysilicon layer, forming a second photoresist layer on the polysilicon layer, creating a second pattern on the second photoresistlayer, and implanting ions into the portions of the polysilicon layer that are not covered by the second photoresist layer, removing the second photoresist layer from the polysilicon layer, and removing portions of the polysilicon layer using an etchant.
    Type: Application
    Filed: February 6, 2012
    Publication date: August 8, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Yen HSIEH, Ming-Ching CHANG, Chia-Wei CHANG, Chao-Cheng CHEN, Chun-Hung LEE, Dai-Lin WU
  • Publication number: 20130202018
    Abstract: A power line communication (PLC) method includes the steps of: programming a registration code into a micro inverter; enabling a data collector to execute a register step, which includes an operation of registering and saving the registration code to a server, through internet; enabling the data collector to send a message to the server through the internet; enabling the server to deliver an authentication code, which is relative to the registration code, to the data collector through the internet according to the message; and enabling the data collector and the micro inverter to identify each other via a power line based on the authentication code.
    Type: Application
    Filed: September 14, 2012
    Publication date: August 8, 2013
    Inventors: Sheng-Hua Li, Chi-Hsiung Dai, Hao-Hsuan Chen, Chia-Wei Chang