Abstract: A method includes determining, at a network routing device, an average packet drop rate for a plurality of aggregations of packet flows. The method also determines a threshold packet drop rate based on the average packet drop rate, a current packet drop rate for a select aggregation of the plurality of aggregations, and whether at least one packet flow of the select aggregation is potentially subject to a denial-of-service attack based on a comparison of the current packet drop rate to the threshold packet drop rate.

Abstract: A group keypad structure in compliance with a standard keyboard installation includes group keypads corresponding to characters of a standard keyboard input method; for example, the structure includes ten group keypads installed from left to right on a base, and the ten group keypads include characters of “Q, A, Z”, “W, S, X”, “E, D, C”, “R, F, V”, “T, G, B”, “Y, H, N”, “U, J, M”, “I, K, ,”, “O, L, .” and “P, ;, /” respectively, and further includes ten numeric characters “1˜0”, so as to achieve the effects of reducing the area of a keyboard, shortening the moving distance of a user's fingers, providing an easy and convenient carry, complying with the user's using habit, and improving the input speed.

Abstract: An apparatus for mounting a pellicle onto a mask is provided. In one embodiment, the apparatus comprises a base provided with a track; a dummy plate holder coupled to the base, the dummy plate holder for receiving a dummy plate having an elevated portion on one side thereof; a mask holder for receiving a mask, the mask holder slidably coupled to the base; a pellicle holder for receiving a pellicle frame, the pellicle holder slidably coupled to the base; and drive means being adapted to drive the pellicle holder along the track towards the dummy plate holder, wherein during operation when the pellicle frame is mounted onto the mask causing the mask to contact the dummy plate, the mounting pressure in the mask is distributed by way of the elevated portion in the dummy plate, thus reducing distortion in the mask.

Abstract: A furniture bow beam structure and a manufacturing method thereof. By means of pressing, metal board materials are processed into different assembling members and connecting members. The assembling members and connecting members respectively have curvatures and configurations in conformity with different sections of the beam structure. Each assembling member has an opening that obliquely diverges to one side in width. The connecting member is connected to the opening and mated with the assembling member to form a hollow tubular support. Multiple supports are then connected with each other and rectified to form a complete beam structure with desired curvatures and shapes for connecting with other furniture components.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate layer over a substrate, forming a hard mask layer over a gate layer, forming a first material layer over the hard mask layer, forming a patterned photoresist layer having an opening over the first material layer, etching the first material layer through a cycle including forming a second material layer over the semiconductor device and etching the first and second material layers, repeating the cycle until the hard mask layer is exposed by a reduced opening, the reduced opening formed in a last cycle, etching the hard mask layer beneath the second opening to expose the gate layer, and patterning the gate layer using the hard mask layer. An etching selectivity of the first and second material layers is smaller than an etching selectivity of the second material layer and the photoresist layer.

Abstract: A stack structure of circuit boards embedded with semiconductor chips is proposed. At least two circuit boards are provided. Each of the circuit boards includes circuit layers formed on surfaces thereof and at least one opening embedded with a semiconductor chip, wherein, the circuit layers have a plurality of conductive structures and electrically conductive pads, and the semiconductor chip has a plurality of electrode pads, and the conductive structures of the circuit layers are electrically conductive to the electrode pads of the semiconductor chip. At least one adhesive layer is formed between the two circuit boards and disposed with a conductive material corresponding in position to the electrically conductive pads of the circuit boards. Thus, a conductive path can be formed by the conductive material between the electrically conductive pads of the circuit boards, thereby establishing electrical connection between the two circuit boards.

Abstract: A circuit board structure having a capacitor array and an embedded electronic component and a method for fabricating the same are proposed. Two carrier boards and a high dielectric constant material layer are provided, wherein the carrier boards have electronic components embedded therein and one surface of each carrier board has a plurality of electrode plates. The two carrier boards are laminated with the dielectric constant material layer interposed between them. The electrode plates on the surfaces of the carrier boards are opposite to each other across the high dielectric constant material layer to constitute a capacitor array. Therefore, the capacitor assembly for design of electronic devices is provided.

Abstract: An improved surface mounting method applied in a semiconductor package process is provided, wherein the method comprises the following steps: First a substrate having at least one pad set on one surface of the substrate is provided. Then a mask having at least one opening associated with one of the at least one pad is set on the substrate, wherein each opening is separated into a plurality of sub-openings by a segregator to expose the pad. Subsequently, a printing process is conducted to form a conductive layer on each pad. After removing the mask, a passive device is set on the conductive layer over the pad, and a heating treatment is conducted to fix the passive device on the pad.

Abstract: A stack structure of circuit boards embedded with semiconductor components therein is proposed, which includes at least two semiconductor components embedded circuit boards, a plurality of conductive bumps, and at least one adhesive layer. The circuit boards are each formed with a circuit layer having a plurality of electrical connection pads. The conductive bumps are formed on the electrical connection pads of at least one of the circuit boards. The adhesive layer is formed between the circuit boards such that a portion of the adhesive layer between the conductive bumps and the electrical connection pads, or between the opposing conductive bumps, forms a conductive channel and thereby forms an electrical connection between the circuit boards.

Abstract: The Phosphorus-containing bisphenols and preparing method thereof are disclosed. A method for producing the phosphorus-containing bisphenol of the general formula (1) includes reacting compounds respectively defined by a general formula (a), (b), (c) and an acid catalyst to yield compounds of phosphorus-containing bisphenol.

Abstract: A carrier structure for a semiconductor chip and a method for manufacturing the same are disclosed. The method includes the following steps: providing a carrier board having at least one through cavity, wherein a removable film is formed on the surface of the carrier board, and a semiconductor chip is temporarily fixed in the through cavity by the removable film; filling the gap between the through cavity of the carrier board and the semiconductor chip with an adhesive material in order to fix the semiconductor chip; and removing the removable film. The disclosed method can reduce the alignment error resulted from the tiny shift of the semiconductor chip caused by jitters before the semiconductor is fixed in the cavity, thereby to increase the accuracy of the alignment, to facilitate fine wiring, and to meet the trend toward compact size of semiconductor packages.

Abstract: A series of novel phosphorus-containing compounds having the following formula are disclosed: wherein R1-R12, A, B, D, X, and Y are as defined in the specification. A process for the preparation of the compound of formula (1), a curing agent, and a flame resistant epoxy resin and a preparation process thereof are also provided.

Abstract: A controllable delay line includes an anti-jitter unit, a dependent current source, a first current mirror, a second current mirror, a regulation capacitor, a compensation capacitor and an output buffer unit. The anti-jitter unit receives a first bias voltage and produces a second bias voltage based on the first bias voltage. When the voltage source used in the controllable delay line has a variation, the second bias voltage varies therewith. The regulation capacitor is used for reducing the variation of the voltage difference between the voltage source and a node voltage of the first current source. The compensation capacitor is used for reducing the influence of a transition of the input signal of the output buffer unit on the node voltage, so as to lower the jitter amount of the output signal of the output buffer unit.

Abstract: A series of novel phosphorus-containing compounds having the following formula are disclosed: wherein Q, R5, Ar1, Ar2, A, and B are as defined in the specification. The present invention provides a process for the preparation of the compound of formula (I). The present invention also provides a compound of formula (PA) and a process for preparing the same. The present invention further provides a compound of formula (PI) and a process for preparing the same.

Abstract: The present invention relates to a stacked package module and a method for fabricating the same. The stacked package module comprises: a first package structure, a second package structure, a ceramic-surfaced aluminum plate, and a metal paste. Herein, the ceramic-surfaced aluminum plate has a plurality of through holes filled with the metal paste to correspond with and electrically connect the first conductive pads of the first package structure and the second conductive pads of the second package structure; and the ceramic-surfaced aluminum plate further has a first cavity to receive a chip. Besides, the present invention provides a stacked package module, which can avoid warpage, omit the process for soldering, favor the shrinkage of size and pitch of the conductive pads, and also can reduce the height of the package.

Abstract: A signal routing method adapted to a DWA structure is provided. The signal routing method at least includes following steps. An M-bit input digital signal is provided. The odd bit in the input digital signal is routed into a low-bit signal of an output digital signal, and the even bit in the input digital signal is routed into a high-bit signal of the output digital signal, wherein the output digital signal has M bits.

Abstract: A stack structure of circuit boards embedded with semiconductor chips is proposed. At least two circuit boards are provided. Each of the circuit boards includes circuit layers formed on surfaces thereof and at least one opening embedded with a semiconductor chip, wherein, the circuit layers have a plurality of conductive structures and electrically conductive pads, and the semiconductor chip has a plurality of electrode pads, and the conductive structures of the circuit layers are electrically conductive to the electrode pads of the semiconductor chip. At least one adhesive layer is formed between the two circuit boards and disposed with a conductive material corresponding in position to the electrically conductive pads of the circuit boards. Thus, a conductive path can be formed by the conductive material between the electrically conductive pads of the circuit boards, thereby establishing electrical connection between the two circuit boards.