Patents by Inventor Chia-Wei Wu

Chia-Wei Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11126068
    Abstract: An optical system is provided, including a fixed part, a movable part, a first optical element, a driving assembly, and a circuit assembly. The movable part is movable relative to the fixed part. The first optical element is connected to the movable part. The driving assembly is configured for driving the movable part to move relative to the fixed part. The circuit assembly is electrically connected to the driving assembly.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: September 21, 2021
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Sung-Mao Tsai, Liang-Ting Ho, Chih-Wei Weng, Chia-Che Wu, Sin-Jhong Song
  • Patent number: 11121031
    Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: September 14, 2021
    Assignee: XINTEC INC.
    Inventors: Chia-Sheng Lin, Hui-Hsien Wu, Jian-Hong Chen, Tsang-Yu Liu, Kuei-Wei Chen
  • Publication number: 20210278623
    Abstract: An optical element drive mechanism is provided. The optical element drive mechanism includes an immovable part, a movable part, and a drive assembly. The movable part is movable relative to the immovable part. The movable part holds an optical element with an optical axis. The drive assembly drives the movable part to move relative to the immovable part. At least part of the drive assembly is disposed on the immovable part.
    Type: Application
    Filed: November 10, 2020
    Publication date: September 9, 2021
    Inventors: Shang-Yu HSU, Meng-Ting LIN, Shih-Wei HUNG, Yu-Huai LIAO, Chia-Che WU, Mao-Gen JIAN, Chih-Wei WENG
  • Publication number: 20210280444
    Abstract: A substrate processing apparatus includes a process station for processing a substrate; a cassette station integrated with the process station; a substrate carriage equipped for transferring the substrate between said process station and the cassette station through a passage located at an interface between the process station and said cassette station; and a substrate scanner equipped at said interface between the process station and the cassette station for capturing surface image data during transportation of the substrate that passes through the passage.
    Type: Application
    Filed: March 26, 2020
    Publication date: September 9, 2021
    Inventors: Ming-Che Lai, Hua-Wei Peng, Chia-He Cheng, Ming-Tso Chen, Chao-Chi Lu, Hsin-Hsu Lin, Kuo-Tsai Lo, Kao-Hua Wu, Huan-Hsin Yeh
  • Patent number: 11114566
    Abstract: A semiconductor device includes a substrate, a first fin, a second fin, a dummy fin, a first metal gate, a second metal gate, and an isolation structure. The first, the second and the dummy fins are on the substrate, and the dummy fin is disposed between the first fin and the second fin. The first metal gate and the second metal gate are over the first fin and the second fin, respectively. The isolation structure is on the dummy fin, and the dummy fin and the isolation structure separate the first metal gate and the second metal gate.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: September 7, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Chang Lin, Kai-Chieh Yang, Chia-Wei Su, Jia-Ni Yu, Wei-Hao Wu, Chih-Hao Wang
  • Patent number: 11107725
    Abstract: The present disclosure provides an interconnect structure, including a first metal line, a conductive contact over the first metal line, including a first portion, a second portion over the first portion, wherein a bottom width of the second portion is greater than a top width of the first portion, and a third portion over the second portion, wherein a bottom width of the third portion is greater than a top width of the second portion, a sacrificial bilayer, including a first sacrificial layer, wherein a first portion of the first sacrificial layer is under a coverage of a vertical projection area of the first portion of the conductive contact, and a second sacrificial layer over the first sacrificial layer, and a dielectric layer over a top surface of the second sacrificial layer.
    Type: Grant
    Filed: September 20, 2020
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsiang-Wei Liu, Wei-Chen Chu, Chia-Tien Wu, Tai-I Yang
  • Patent number: 11106000
    Abstract: A driving mechanism for supporting an optical member is provided, including a base, a frame, a movable portion, a driving module, and an adhesive member. The base includes a plurality of first sidewalls, and at least one recess is formed on the first sidewalls. The frame includes a plurality of second sidewalls, and at least one opening is formed on the second sidewalls. The base and the frame form a hollow box, and the opening corresponds to the recess. The movable portion and the driving module are disposed in the hollow box. The driving module can drive the movable portion to move relative to the base. The adhesive member is accommodated in the opening and the recess, and extended along the first sidewalls. The adhesive member is disposed between the first sidewalls and the second sidewalls.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: August 31, 2021
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Bing-Ru Song, Yi-Ho Chen, Chia-Pin Hsu, Chih-Wei Weng, Shin-Hua Chen, Chien-Lun Huang, Chao-Chun Chang, Shou-Jen Liu, Kun-Shih Lin, Nai-Wen Hsu, Yu-Cheng Lin, Shang-Yu Hsu, Yu-Huai Liao, Yi-Hsin Nieh, Shih-Ting Huang, Kuo-Chun Kao, Fu-Yuan Wu
  • Patent number: 11101238
    Abstract: A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: August 24, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Kai Liu, Chun-Lin Lu, Kai-Chiang Wu, Shih-Wei Liang, Ching-Feng Yang, Yen-Ping Wang, Chia-Chun Miao
  • Patent number: 11081350
    Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: August 3, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Jou Lian, Yao-Wen Hsu, Neng-Jye Yang, Li-Min Chen, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang
  • Publication number: 20210159235
    Abstract: A memory device and a method for forming the same are provided. The method includes forming a plurality of gate structures on a substrate, forming a first spacer on opposite sides of the gate structures, filling a dielectric layer between adjacent first spacers, forming a metal silicide layer on the gate structures, conformally forming a spacer material layer over the metal silicide layer, the first spacer layer and the dielectric layer, and performing an etch back process on the spacer material layer to form a second spacer on opposite sides of the metal silicide layer.
    Type: Application
    Filed: November 22, 2019
    Publication date: May 27, 2021
    Inventors: Yi-Tsung TSAI, Chia-Wei WU, Chih-Hao LIN, Chien-Chih LI
  • Patent number: 11018049
    Abstract: A manufacturing method of an isolation structure includes the following steps. A semiconductor substrate is provided. A trench is formed in the semiconductor substrate. A first film forming process is performed to form a first dielectric layer conformally on the semiconductor substrate and conformally in the trench. An annealing process is performed to densify the first dielectric layer and convert the first dielectric layer into a second dielectric layer. A thickness of the second dielectric layer is less than a thickness of the first dielectric layer. A second film forming process is performed after the annealing process to form a third dielectric layer on the second dielectric layer and in the trench. The trench is filled with the second dielectric layer and the third dielectric layer.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: May 25, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Shan Su, Chia-Wei Wu
  • Publication number: 20200401041
    Abstract: A method includes forming a tri-layer. The tri-layer includes a bottom layer; a middle layer over the bottom layer; and a top layer over the middle layer. The top layer includes a photo resist. The method further includes removing the top layer; and removing the middle layer using a chemical solution. The chemical solution is free from potassium hydroxide (KOH), and includes at least one of a quaternary ammonium hydroxide and a quaternary ammonium fluoride.
    Type: Application
    Filed: August 31, 2020
    Publication date: December 24, 2020
    Inventors: Li-Min Chen, Kuo Bin Huang, Neng-Jye Yang, Chia-Wei Wu, Jian-Jou Lian
  • Patent number: 10867803
    Abstract: A method of manufacturing a semiconductor device includes exposing a material to a semi-aqueous etching solution. The semi-aqueous etching solution comprises a solvent which chelates with the material and acts as a catalyst between the etching driving force and the material. As such, the etching driving force may be used to remove the material.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wen Hsu, Jian-Jou Lian, Neng-Jye Yang, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang, Li-Min Chen
  • Patent number: 10861855
    Abstract: A semiconductor device and method of manufacturing the same is provided in the present invention. The method includes the step of forming first mask patterns on a substrate, wherein the first mask patterns extend in a second direction and are spaced apart in a first direction to expose a portion of first insulating layer, removing the exposed first insulating layer to form multiple recesses in the first insulating layer, performing a surface treatment to the recess surface, filling up the recesses with a second insulating layer and exposing a portion of the first insulating layer, removing the exposed first insulating layer to form a mesh-type isolation structure, and forming storage node contact plugs in the openings of mesh-type isolation structure.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: December 8, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Shih-Fang Tzou, Chien-Cheng Tsai, Chih-Chi Cheng, Chia-Wei Wu, Ger-Pin Lin
  • Patent number: 10817047
    Abstract: A tracking system is disclosed. The tracking system comprises a head-mounted display (HMD) worn on a head of a user and configured to virtualize a body movement of the user in a virtual environment; and a plurality of sensors worn on feet of the user configured to determine body information of the user according to the body movement of the user, and transmit the determined body information to the HMD; wherein the HMD virtualizes the body movement of the user according to the determined body information; wherein the body information is related to a plurality of mutual relationships between the plurality of sensors and the HMD.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: October 27, 2020
    Assignee: XRSpace CO., LTD.
    Inventors: Peter Chou, Chun-Wei Lin, Yi-Kang Hsieh, Chia-Wei Wu
  • Patent number: 10761423
    Abstract: A method includes forming a tri-layer. The tri-layer includes a bottom layer; a middle layer over the bottom layer; and a top layer over the middle layer. The top layer includes a photo resist. The method further includes removing the top layer; and removing the middle layer using a chemical solution. The chemical solution is free from potassium hydroxide (KOH), and includes at least one of a quaternary ammonium hydroxide and a quaternary ammonium fluoride.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Min Chen, Kuo Bin Huang, Neng-Jye Yang, Chia-Wei Wu, Jian-Jou Lian
  • Publication number: 20200266065
    Abstract: A middle layer removal method is provided. The method includes providing a substrate having a structure formed on the substrate, and forming a spacer layer on the structure. The method includes forming a mask layer over the spacer layer, the mask layer including a first layer, a second layer over the first layer, and a third layer over the second layer. The method also includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer to form an opening to expose a bottom surface of the second layer. The method further includes removing the second layer using a wet etchant.
    Type: Application
    Filed: May 8, 2020
    Publication date: August 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nai-Chia CHEN, Wan Hsuan HSU, Chia-Wei WU, Neng-Jye YANG, Chun-Li CHOU
  • Publication number: 20200235101
    Abstract: A semiconductor device and method of manufacturing the same is provided in the present invention. The method includes the step of forming first mask patterns on a substrate, wherein the first mask patterns extend in a second direction and are spaced apart in a first direction to expose a portion of first insulating layer, removing the exposed first insulating layer to form multiple recesses in the first insulating layer, performing a surface treatment to the recess surface, filling up the recesses with a second insulating layer and exposing a portion of the first insulating layer, removing the exposed first insulating layer to form a mesh-type isolation structure, and forming storage node contact plugs in the openings of mesh-type isolation structure.
    Type: Application
    Filed: April 7, 2020
    Publication date: July 23, 2020
    Inventors: Li-Wei Feng, Shih-Fang Tzou, Chien-Cheng Tsai, Chih-Chi Cheng, Chia-Wei Wu, Ger-Pin Lin
  • Publication number: 20200185505
    Abstract: A semiconductor device includes a substrate having at least a trench formed therein. A conductive material fills a lower portion of the trench. A barrier layer is between the conductive material and the substrate. An insulating layer is in the trench and completely covers the conductive material and the barrier layer, wherein a portion of the insulating layer covering the barrier layer has a bird's peak profile.
    Type: Application
    Filed: February 17, 2020
    Publication date: June 11, 2020
    Inventors: Chia-Wei Wu, Ting-Pang Chung, Tien-Chen Chan, Shu-Yen Chan
  • Patent number: 10658365
    Abstract: A semiconductor device and method of manufacturing the same is provided in the present invention. The method includes the step of forming first mask patterns on a substrate, wherein the first mask patterns extend in a second direction and are spaced apart in a first direction to expose a portion of first insulating layer, removing the exposed first insulating layer to form multiple recesses in the first insulating layer, performing a surface treatment to the recess surface, filling up the recesses with a second insulating layer and exposing a portion of the first insulating layer, removing the exposed first insulating layer to form a mesh-type isolation structure, and forming storage node contact plugs in the openings of mesh-type isolation structure.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: May 19, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Shih-Fang Tzou, Chien-Cheng Tsai, Chih-Chi Cheng, Chia-Wei Wu, Ger-Pin Lin