Patents by Inventor Chia-Wei Wu

Chia-Wei Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10490556
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, wherein a width of the second trench is greater than a width of the first trench; forming a first liner, a second liner, and a third liner in the first trench and the second trench; performing a surface treatment process to lower stress of the third liner; and planarizing the third liner, the second liner, and the first liner to form a first isolation structure and a second isolation structure.
    Type: Grant
    Filed: July 29, 2018
    Date of Patent: November 26, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Shan Su, Chia-Wei Wu, Ting-Pang Chung
  • Patent number: 10483108
    Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Jou Lian, Yao-Wen Hsu, Neng-Jye Yang, Li-Min Chen, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang
  • Publication number: 20190279876
    Abstract: A method of manufacturing a semiconductor device includes exposing a material to a semi-aqueous etching solution. The semi-aqueous etching solution comprises a solvent which chelates with the material and acts as a catalyst between the etching driving force and the material. As such, the etching driving force may be used to remove the material.
    Type: Application
    Filed: May 30, 2019
    Publication date: September 12, 2019
    Inventors: Yao-Wen Hsu, Jian-Jou Lian, Neng-Jye Yang, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang, Li-Min Chen
  • Patent number: 10332889
    Abstract: A method of manufacturing a semiconductor device is provided, which includes the steps of providing a capacitor structure, forming a conductive layer on the capacitor structure, performing a hydrogen doping process to the conductive layer, forming a metal layer on the conductive layer after the hydrogen doping process, and patterning the metal layer and the conductive layer to forma top electrode plate.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: June 25, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Ger-Pin Lin, Tien-Chen Chan, Shu-Yen Chan, Chi-Mao Hsu, Shih-Fang Tzou, Ting-Pang Chung, Chia-Wei Wu
  • Patent number: 10312106
    Abstract: A method of manufacturing a semiconductor device includes exposing a material to a semi-aqueous etching solution. The semi-aqueous etching solution comprises a solvent which chelates with the material and acts as a catalyst between the etching driving force and the material. As such, the etching driving force may be used to remove the material.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: June 4, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wen Hsu, Jian-Jou Lian, Neng-Jye Yang, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang, Li-Min Chen
  • Publication number: 20190081047
    Abstract: A semiconductor device and method of manufacturing the same is provided in the present invention. The method includes the step of forming first mask patterns on a substrate, wherein the first mask patterns extend in a second direction and are spaced apart in a first direction to expose a portion of first insulating layer, removing the exposed first insulating layer to form multiple recesses in the first insulating layer, performing a surface treatment to the recess surface, filling up the recesses with a second insulating layer and exposing a portion of the first insulating layer, removing the exposed first insulating layer to form a mesh-type isolation structure, and forming storage node contact plugs in the openings of mesh-type isolation structure.
    Type: Application
    Filed: August 2, 2018
    Publication date: March 14, 2019
    Inventors: Li-Wei Feng, Shih-Fang Tzou, Chien-Cheng Tsai, Chih-Chi Cheng, Chia-Wei Wu, Ger-Pin Lin
  • Publication number: 20190074210
    Abstract: A manufacturing method of an isolation structure includes the following steps. A semiconductor substrate is provided. A trench is formed in the semiconductor substrate. A first film forming process is performed to form a first dielectric layer conformally on the semiconductor substrate and conformally in the trench. An annealing process is performed to densify the first dielectric layer and convert the first dielectric layer into a second dielectric layer. A thickness of the second dielectric layer is less than a thickness of the first dielectric layer. A second film forming process is performed after the annealing process to form a third dielectric layer on the second dielectric layer and in the trench. The trench is filled with the second dielectric layer and the third dielectric layer.
    Type: Application
    Filed: July 6, 2018
    Publication date: March 7, 2019
    Inventors: Yu-Shan Su, Chia-Wei Wu
  • Publication number: 20190074280
    Abstract: A method of manufacturing a semiconductor device is provided, which includes the steps of providing a capacitor structure, forming a conductive layer on the capacitor structure, performing a hydrogen doping process to the conductive layer, forming a metal layer on the conductive layer after the hydrogen doping process, and patterning the metal layer and the conductive layer to forma top electrode plate.
    Type: Application
    Filed: April 12, 2018
    Publication date: March 7, 2019
    Inventors: Ger-Pin Lin, Tien-Chen Chan, Shu-Yen Chan, Chi-Mao Hsu, Shih-Fang Tzou, Ting-Pang Chung, Chia-Wei Wu
  • Publication number: 20190064658
    Abstract: A method includes forming a tri-layer. The tri-layer includes a bottom layer; a middle layer over the bottom layer; and a top layer over the middle layer. The top layer includes a photo resist. The method further includes removing the top layer; and removing the middle layer using a chemical solution. The chemical solution is free from potassium hydroxide (KOH), and includes at least one of a quaternary ammonium hydroxide and a quaternary ammonium fluoride.
    Type: Application
    Filed: October 3, 2017
    Publication date: February 28, 2019
    Inventors: Li-Min Chen, Kuo Bin Huang, Neng-Jye Yang, Chia-Wei Wu, Jian-Jou Lian
  • Patent number: 10204915
    Abstract: A method of forming a dynamic random access memory (DRAM) includes the following steps. A substrate includes a memory area and a logic area. A stacked structure is formed on the substrate of the memory area and a gate structure is formed on the substrate of the logic area. A first mask layer is formed on the stacked structure and the gate structure. A densification process is performed to densify the first mask layer. A second mask layer is formed on the first mask layer. A part of the second mask layer and a part of the first mask layer are removed to form a first spacer on sidewalls of the gate structure.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: February 12, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Shan Su, Chia-Wei Wu
  • Publication number: 20190035637
    Abstract: A method of manufacturing a semiconductor device includes exposing a material to a semi-aqueous etching solution. The semi-aqueous etching solution comprises a solvent which chelates with the material and acts as a catalyst between the etching driving force and the material. As such, the etching driving force may be used to remove the material.
    Type: Application
    Filed: November 1, 2017
    Publication date: January 31, 2019
    Inventors: Yao-Wen Hsu, Jian-Jou Lian, Neng-Jye Yang, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang, Li-Min Chen
  • Publication number: 20180315595
    Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.
    Type: Application
    Filed: October 3, 2017
    Publication date: November 1, 2018
    Inventors: Jian-Jou Lian, Yao-Wen Hsu, Neng-Jye Yang, Li-Min Chen, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang
  • Publication number: 20180239449
    Abstract: An active stylus that is applicable to a touch panel. The touch panel comprises driving electrodes and sensing electrodes. Each driving electrode transmits a panel driving signal. The sensing electrodes receive the panel driving signal. The active stylus comprises a receiving element receiving the panel driving signal; a sensing module obtaining signal characteristics of the panel driving signal; a signal generator generating a simulated driving signal; a driving element transmitting the simulated driving signal; and a control unit. The control unit uses the signal generator to generate the simulated driving signal, which is synchronous with and identical in phase to the panel driving signal, according to the signal characteristics of the panel driving signal. Thereby, the touch panel can distinguish the touch of an active stylus from the touch of a hand and realize a multi-point touch control function in a mutual-capacitance mode.
    Type: Application
    Filed: May 18, 2017
    Publication date: August 23, 2018
    Inventors: Tse Yen LIN, Chi Chin CHEN, Wen Yi LEE, Chia Wei WU
  • Publication number: 20180212030
    Abstract: A semiconductor device and a method of forming the same are disclosed. First, a substrate having a main surface is provided. At least a trench is formed in the substrate. A barrier layer is formed in the trench and a conductive material is formed on the barrier layer and filling up the trench. The barrier layer and the conductive material are then recessed to be lower than the upper surface of the substrate. After that, an oxidation process is performed to oxidize the barrier layer and the conductive material thereby forming an insulating layer.
    Type: Application
    Filed: January 18, 2018
    Publication date: July 26, 2018
    Inventors: Chia-Wei Wu, Ting-Pang Chung, Tien-Chen Chan, Shu-Yen Chan
  • Publication number: 20170140056
    Abstract: Methods and systems for generating influence scores are disclosed. A plurality of opinions of a selected topic are retrieved from a database. Influencers each associated with at least one opinion from the plurality of opinions are determined using the processor. A score is automatically generated for each influencer using the processor, the score related to the selected topic.
    Type: Application
    Filed: January 30, 2017
    Publication date: May 18, 2017
    Inventors: Chia-Wei Wu, Claire Cardie, Laurence Levy, Shaomei Wu, Vladimir Dmitrievich Barash, David Rusell Pierce
  • Patent number: 9558273
    Abstract: Methods and systems for generating influence scores are disclosed. A plurality of opinions of a selected topic are retrieved from a database. Influencers each associated with at least one opinion from the plurality of opinions are determined using the processor. A score is automatically generated for each influencer using the processor, the score related to the selected topic.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: January 31, 2017
    Assignee: Appinions Inc.
    Inventors: Chia-Wei Wu, Claire Cardie, Laurence Levy, Shaomei Wu, Vladimir Dmitrievich Barash, David Rusell Pierce
  • Publication number: 20170017343
    Abstract: A noise reduction capacitive touch panel comprises a sensing area, a non-sensing area, a main body, a plurality of driving electrodes, a plurality of driving electrode wires, a plurality of sensing electrodes, a plurality of sensing electrode wires, at least one noise sensing electrodes and at least noise sensing electrode wires. The sensing area is located in the middle of the panel and the rest area of the panel is the non-sensing area. The main body is a flat board having a normal line. The driving electrodes are strip electrodes and disposed on the main body. The driving electrodes are perpendicular to the normal line. The driving electrodes wires are disposed on the main body. The sensing electrodes are strip electrodes and disposed on the main body. Capacitive coupling is occurred between the driving electrodes and the sensing electrodes because there is a distance between them.
    Type: Application
    Filed: July 17, 2015
    Publication date: January 19, 2017
    Inventors: Chi Chin CHEN, Wen Yi LEE, Chia Wei WU, Chang Kuang CHUNG, Tse Yen LIN
  • Patent number: 9465478
    Abstract: A projected capacitive touch panel comprises a touch control integrated circuit, sensing electrodes, driving electrodes, a MCU, a AC signal generator, a sensing bus, and a driving bus. The driving electrodes are made of high resistance material. One driving electrodes is selected by MCU based on firmware program as selected driving electrode. A low voltage AC signal is generated by the AC signal generator. The AC signal is transmitted to the selected driving electrode and its adjacent two driving electrodes via the driving bus. The rest of driving electrodes are connected to a fixed DC level. Providing the same AC signal to three driving electrodes simultaneously can induce higher sensing signal in the sensing electrodes.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: October 11, 2016
    Assignee: INPUTEK CO., LTD.
    Inventors: Chi Chin Chen, Wen Yi Lee, Tse Yen Lin, Chia Wei Wu
  • Publication number: 20160110007
    Abstract: A projected capacitive touch panel comprises a touch control integrated circuit, sensing electrodes, driving electrodes, a MCU, a AC signal generator, a sensing bus, and a driving bus. The driving electrodes are made of high resistance material. One driving electrodes is selected by MCU based on firmware program as selected driving electrode. A low voltage AC signal is generated by the AC signal generator. The AC signal is transmitted to the selected driving electrode and its adjacent two driving electrodes via the driving bus. The rest of driving electrodes are connected to a fixed DC level. Providing the same AC signal to three driving electrodes simultaneously can induce higher sensing signal in the sensing electrodes.
    Type: Application
    Filed: October 17, 2014
    Publication date: April 21, 2016
    Inventors: Chi Chin CHEN, Wen Yi LEE, Tse Yen LIN, Chia Wei WU
  • Patent number: 9246015
    Abstract: A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: January 26, 2016
    Assignee: Macronix International Co., Ltd.
    Inventors: Tzu-Hsuan Hsu, Yen-Hao Shih, Chia-Wei Wu