Patents by Inventor Chia-Yu Chen

Chia-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus to identify a live face image using a thermal radiation sensor and a visual radiation sensor
    Patent number: 9886640
    Abstract: A method, system and computer program product are disclosed that comprise capturing first image data of a person's face using at least one sensor responsive in a band of infrared wavelengths and capturing second image data of the person's face using the at least one sensor responsive in a band of visible wavelengths; extracting image features in the image data and detecting face regions; applying a similarity analysis to image feature edge maps extracted from the first and the second image data; and recognizing a presence of a live face image after regions found in the first image data pass a facial features classifier. Upon recognizing the presence of the live face image, additional operations can include verifying the identity of the person as an authorized person and granting the person access to a resource.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: February 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Chia-Yu Chen, Pierce I-Jen Chuang, Li-Wen Hung, Jui-Hsin Lai
  • WRENCH ADJUSTABLE IN HEAD ANGLE
    Publication number: 20180001445
    Abstract: A wrench adjustable in head angle includes a pull lever having one end provided with an accommodating groove for receiving a spring and a resisting pin. The resisting pin is fitted thereon with a push member, and the pull lever is pivotally connected with a driving head. The resisting pin has one end elastically pushed by the spring to be engaged with one end of the driving head and the resisting pin is engaged with the push member. The push member can be pushed to actuate the resisting pin to press the spring, letting the resisting pin disengaged from the driving head for adjusting the angle of the driving head, convenient in operation.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 4, 2018
    Inventor: Chia-Yu CHEN
  • Dual FIN integration for electron and hole mobility enhancement
    Patent number: 9859281
    Abstract: A technique for forming a semiconductor device is provided. Sacrificial mandrels are formed over a hardmask layer on a semiconductor layer. Spacers are formed on sidewalls of the sacrificial mandrels. The sacrificial mandrels are removed to leave the spacers. A masking process leaves exposed a first set of spacers with a second set protected. In response to the masking process, a first fin etch process forms a first set of fins in the semiconductor layer via first set of spacers. The first set of fins has a vertical sidewall profile. Another masking process leaves exposed the second set of spacers with the first set of spacers and the first set of fins protected. In response to the other masking process, a second fin etch process forms a second set of fins in semiconductor layer using the second set of spacers. The second set of fins has a trapezoidal sidewall profile.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chia-Yu Chen, Zuoguang Liu, Miaomiao Wang, Tenko Yamashita
  • GRAPH METHOD FOR SYSTEM SENSITIVITY ANALYSES
    Publication number: 20170344558
    Abstract: A computer-implemented method, computer program product, and system for determination of critical parts and component correlations in a circuit using a correlation graph and centrality analysis including; receiving a circuit layout portion of a larger circuit layout, converting the circuit layout portion into a correlation graph representing components as nodes and connecting wires as edges, determining, using ground truth and Naïve Bayes to determine correlation weighting, scaling the correlation graph to represent the larger circuit, and presenting the larger correlation graph on a graphical user interface (GUI).
    Type: Application
    Filed: May 26, 2016
    Publication date: November 30, 2017
    Inventors: Chia-Yu Chen, Pei-Yun Hsueh, Jui-Hsin Lai, Yinglong Xia
  • HETEROGENEOUS RUNAHEAD CORE FOR DATA ANALYTICS
    Publication number: 20170344485
    Abstract: Techniques that facilitate heterogeneous runahead processing for a processor core are provided. In one example, a first core performs a first execution of a first sequence of instructions, where the first core is communicatively coupled to a first cache memory. A second core performs a second execution of at least a portion of the first sequence of instructions and a first determination that data associated with the first sequence of instructions fails to be stored in the first cache memory, where the first determination is performed concurrent with the first execution, and the first core executes a second sequence of instructions based on a second determination that the second core is performing the second execution of at least a portion of the first sequence of instructions.
    Type: Application
    Filed: May 25, 2016
    Publication date: November 30, 2017
    Inventors: Chia-Yu Chen, Jungwook Choi, Shu-Jen Han, Yinglong Xia
  • Electrical Components Having Metal Traces With Protected Sidewalls
    Publication number: 20170294499
    Abstract: A component such as a display may have a substrate and thin-film circuitry on the substrate. The thin-film circuitry may be used to form an array of pixels for a display or other circuit structures. Metal traces may be formed among dielectric layers in the thin-film circuitry. Metal traces may be provided with insulating protective sidewall structures. The protective sidewall structures may be formed by treating exposed edge surfaces of the metal traces. A metal trace may have multiple layers such as a core metal layer sandwiched between barrier metal layers. The core metal layer may be formed from a metal that is subject to corrosion. The protective sidewall structures may help prevent corrosion in the core metal layer. Surface treatments such as oxidation, nitridation, and other processes may be used in forming the protective sidewall structures.
    Type: Application
    Filed: September 16, 2016
    Publication date: October 12, 2017
    Inventors: Chang Ming Lu, Chia-Yu Chen, Chih Pang Chang, Ching-Sang Chuang, Hung-Che Ting, Jung Yen Huang, Sheng Hui Shen, Shih Chang Chang, Tsung-Hsiang Shih, Yu-Wen Liu, Yu Hung Chen, Kai-Chieh Wu, Lun Tsai, Takahide Ishii, Chung-Wang Lee, Hsing-Chuan Wang, Chin Wei Hsu, Fu-Yu Teng
  • PURE BORON FOR SILICIDE CONTACT
    Publication number: 20170288035
    Abstract: A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.
    Type: Application
    Filed: June 22, 2017
    Publication date: October 5, 2017
    Inventors: Chia-Yu Chen, Zuoguang Liu, Sanjay C. Mehta, Tenko Yamashita
  • PURE BORON FOR SILICIDE CONTACT
    Publication number: 20170288036
    Abstract: A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.
    Type: Application
    Filed: June 22, 2017
    Publication date: October 5, 2017
    Inventors: Chia-Yu Chen, Zuoguang Liu, Sanjay C. Mehta, Tenko Yamashita
  • Pure boron for silicide contact
    Patent number: 9741813
    Abstract: A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chia-Yu Chen, Zuoguang Liu, Sanjay C. Mehta, Tenko Yamashita
  • Pure boron for silicide contact
    Patent number: 9735248
    Abstract: A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: August 15, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chia-Yu Chen, Zuoguang Liu, Sanjay C. Mehta, Tenko Yamashita
  • Hybrid substrate engineering in CMOS finFET integration for mobility improvement
    Patent number: 9728640
    Abstract: A method for forming a hybrid complementary metal oxide semiconductor (CMOS) device includes orienting a semiconductor layer of a semiconductor-on-insulator (SOI) substrate with a base substrate of the SOI, exposing the base substrate in an N-well region by etching through a mask layer, a dielectric layer, the semiconductor layer and a buried dielectric to form a trench and forming spacers on sidewalls of the trench. The base substrate is epitaxially grown from a bottom of the trench to form an extended region. A fin material is epitaxially grown from the extended region within the trench. The mask layer and the dielectric layer are restored over the trench. P-type field-effect transistor (PFET) fins are etched on the base substrate, and N-type field-effect transistor (NFET) fins are etched in the semiconductor layer.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: August 8, 2017
    Assignee: International Business Machines Corporation
    Inventors: Chia-Yu Chen, Bruce B. Doris, Hong He, Rajasekhar Venigalla
  • Dual fin integration for electron and hole mobility enhancement
    Patent number: 9728537
    Abstract: A technique for forming a semiconductor device is provided. Sacrificial mandrels are formed over a hardmask layer on a semiconductor layer. Spacers are formed on sidewalls of the sacrificial mandrels. The sacrificial mandrels are removed to leave the spacers. A masking process leaves exposed a first set of spacers with a second set protected. In response to the masking process, a first fin etch process forms a first set of fins in the semiconductor layer via first set of spacers. The first set of fins has a vertical sidewall profile. Another masking process leaves exposed the second set of spacers with the first set of spacers and the first set of fins protected. In response to the other masking process, a second fin etch process forms a second set of fins in semiconductor layer using the second set of spacers. The second set of fins has a trapezoidal sidewall profile.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: August 8, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chia-Yu Chen, Zuoguang Liu, Miaomiao Wang, Tenko Yamashita
  • Reducing Noise and Enhancing Readout Throughput in Sensor Array
    Publication number: 20170219519
    Abstract: Frequency division multiplexing-based techniques for FET-based sensor arrays are provided. In one aspect, a sensor device includes: an array of FET-based sensors, wherein the sensors are grouped into multiple channels, and wherein each of the sensors includes an insulator on a substrate, a local gate embedded in the insulator, a channel material over the local embedded gate, and source and drain electrodes in contact with opposite ends of the channel material, and wherein a surface of the channel material is functionalized to react with at least one target molecule. The sensors in a given channel can be modulated (via the local gate) to enable the signal read out from the channel to be divided in the frequency domain based on the different frequencies used to modulate the sensors.
    Type: Application
    Filed: February 3, 2016
    Publication date: August 3, 2017
    Inventors: Chia-Yu Chen, Shu-Jen Han
  • Dual fin integration for electron and hole mobility enhancement
    Patent number: 9704867
    Abstract: A technique for forming a semiconductor device is provided. Sacrificial mandrels are formed over a hardmask layer on a semiconductor layer. Spacers are formed on sidewalls of the sacrificial mandrels. The sacrificial mandrels are removed to leave the spacers. A masking process leaves exposed a first set of spacers with a second set protected. In response to the masking process, a first fin etch process forms a first set of fins in the semiconductor layer via first set of spacers. The first set of fins has a vertical sidewall profile. Another masking process leaves exposed the second set of spacers with the first set of spacers and the first set of fins protected. In response to the other masking process, a second fin etch process forms a second set of fins in semiconductor layer using the second set of spacers. The second set of fins has a trapezoidal sidewall profile.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: July 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chia-Yu Chen, Zuoguang Liu, Miaomiao Wang, Tenko Yamashita
  • GRAPH-BASED ANALYSIS FOR BIO-SIGNAL EVENT SENSING
    Publication number: 20170169591
    Abstract: One or more biological signals are obtained. The one or more biological signals are converted to one or more graph structures. Correlation between two or more of the biological signals are determined using the one or more graph structures. One or more changes in the one or more graph structures within a time window are recorded. A signal graph model is generated based on the recorded changes.
    Type: Application
    Filed: December 11, 2015
    Publication date: June 15, 2017
    Inventors: Chia-Yu Chen, Pei-Yun S. Hsueh, Jui-Hsin Lai, Yinglong Xia
  • RANDOM TELEGRAPH NOISE NATIVE DEVICE FOR TRUE RANDOM NUMBER GENERATOR AND NOISE INJECTION
    Publication number: 20170161022
    Abstract: A method (and system) for generating random numbers includes setting a drain voltage Vd on an MOSFET device to maximize a transconductance of the MOSFET device and setting a gate voltage Vg of the MOSFET device to tune as desired a random number statistical distribution of an output of the MOSFET device> The MOSFET device includes a gate structure with an oxide layer including at least one artificial trapping layer in which carrier traps are designed to occupy a predetermined distance from conduction and valance bands of material of the artificial trapping layer.
    Type: Application
    Filed: December 2, 2015
    Publication date: June 8, 2017
    Inventors: Chia-yu CHEN, Damon Farmer, Suyog Gupta, Shu-jen Han
  • Monolithic integration of a III-V optoelectronic device, a filter and a driving circuit
    Patent number: 9653441
    Abstract: After forming an opening extending through a (100) silicon layer and a buried insulator layer and into a (111) silicon layer of a semiconductor-on-insulator (SOI) substrate, a light-emitting element is formed within the opening. A portion of the (111) silicon layer located beneath the light-emitting element is patterned to form a patterned structure for tuning light emission characteristics and enhancing efficiency of the light-emitting element. Next, at least one field effect transistor (FET) is formed on the (100) silicon layer for driving the light-emitting element.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: May 16, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chia-Yu Chen, Li-Wen Hung, Jui-Hsin Lai, Ko-Tao Lee
  • Silicon nanowire formation in replacement metal gate process
    Patent number: 9647062
    Abstract: Techniques for a semiconductor device are provided. Techniques are directed to forming a semiconductor device by: forming a fin structure in a substrate, forming a protective layer over an upper portion of the fin structure, the protective layer having an etch selectivity with respect to a material of the fin structure, and performing an undercut etch so as to remove a lower portion of the fin structure below the protective layer, thereby defining a nanowire structure from the fin structure.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: May 9, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chia-Yu Chen, Zuoguang Liu, Tenko Yamashita
  • TIGHTLY COUPLED PROCESSOR ARRAYS USING COARSE GRAINED RECONFIGURABLE ARCHITECTURE WITH ITERATION LEVEL COMMITS
    Publication number: 20170123795
    Abstract: An apparatus and method for supporting simultaneous multiple iterations (SMI) in a course grained reconfigurable architecture (CGRA). In support of SMI, the apparatus includes: Hardware structures that connect all of multiple processing engines (PEs) to a load-store unit (LSU) configured to keep track of which compiled program code iterations have completed, which ones are in flight and which are yet to begin, and a control unit including hardware structures that are used to maintain synchronization and initiate and terminate loops within the PEs. SMI permits execution of the next instruction within any iteration (in flight). If instructions from multiple iterations are ready for execution (and are pre-decoded), then the hardware selects the lowest iteration number ready for execution. If in a particular clock cycle, a loop iteration with a lower iteration number is stalled (i.e.
    Type: Application
    Filed: November 4, 2015
    Publication date: May 4, 2017
    Inventors: Chia-yu Chen, Kailash Gopalakrishnan, Jinwook Oh, Sunil K. Shukla, Vijayalakshmi Srinivasan
  • TIGHTLY COUPLED PROCESSOR ARRAYS USING COARSE GRAINED RECONFIGURABLE ARCHITECTURE WITH ITERATION LEVEL COMMITS
    Publication number: 20170123794
    Abstract: An apparatus and method for supporting simultaneous multiple iterations (SMI) and iteration level commits (ILC) in a course grained reconfigurable architecture (CGRA). The apparatus includes: Hardware structures that connect all of multiple processing engines (PEs) to a load-store unit (LSU) configured to keep track of which compiled program code iterations have completed, which ones are in flight and which are yet to begin, and a control unit including hardware structures that are used to maintain synchronization and initiate and terminate loops within the PEs. The processing elements, LSU and control unit are configured to commit instructions, and save and restore context at loop iteration boundaries. In doing so, the apparatus tracks and buffers state of in-flight iterations, and detects conditions that prevents an iteration from completion.
    Type: Application
    Filed: November 4, 2015
    Publication date: May 4, 2017
    Inventors: Chia-yu Chen, Kailash Gopalakrishnan, Jinwook Oh, Lee M. Saltzman, Sunil K. Shukla, Vijayalakshmi Srinivasan